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[RISCV] Add MIPS extensions (#121394)
Adding two extensions for MIPS p8700 CPU: 1. cmove (conditional move) 2. lsp (load/store pair) The official product page here: https://mips.com/products/hardware/p8700
1 parent b968fd9 commit 0cb7636

22 files changed

+453
-2
lines changed

‎clang/test/Driver/print-supported-extensions-riscv.c

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@@ -157,6 +157,8 @@
157157
// CHECK-NEXT: xcvmac 1.0 'XCVmac' (CORE-V Multiply-Accumulate)
158158
// CHECK-NEXT: xcvmem 1.0 'XCVmem' (CORE-V Post-incrementing Load & Store)
159159
// CHECK-NEXT: xcvsimd 1.0 'XCVsimd' (CORE-V SIMD ALU)
160+
// CHECK-NEXT: xmipscmove 1.0 'XMIPSCMove' (MIPS conditional move instruction(s) (ccmov))
161+
// CHECK-NEXT: xmipslsp 1.0 'XMIPSLSP' (MIPS optimization for hardware load-store bonding)
160162
// CHECK-NEXT: xsfcease 1.0 'XSfcease' (SiFive sf.cease Instruction)
161163
// CHECK-NEXT: xsfvcp 1.0 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)
162164
// CHECK-NEXT: xsfvfnrclipxfqf 1.0 'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)

‎llvm/docs/RISCVUsage.rst

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Original file line numberDiff line numberDiff line change
@@ -459,6 +459,12 @@ The current vendor extensions supported are:
459459
``experimental-Xqcisls``
460460
LLVM implements `version 0.2 of the Qualcomm uC Scaled Load Store extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
461461

462+
``Xmipscmove``
463+
LLVM implements conditional move for the `p8700 processor <https://mips.com/products/hardware/p8700/>` by MIPS.
464+
465+
``Xmipslsp``
466+
LLVM implements load/store pair instructions for the `p8700 processor <https://mips.com/products/hardware/p8700/>` by MIPS.
467+
462468
Experimental C Intrinsics
463469
=========================
464470

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

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Original file line numberDiff line numberDiff line change
@@ -877,6 +877,16 @@ struct RISCVOperand final : public MCParsedAsmOperand {
877877
VK == RISCVMCExpr::VK_RISCV_None;
878878
}
879879

880+
bool isUImm7Lsb000() const {
881+
if (!isImm())
882+
return false;
883+
int64_t Imm;
884+
RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
885+
bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
886+
return IsConstantImm && isShiftedUInt<4, 3>(Imm) &&
887+
VK == RISCVMCExpr::VK_RISCV_None;
888+
}
889+
880890
bool isUImm8Lsb00() const {
881891
if (!isImm())
882892
return false;

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

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Original file line numberDiff line numberDiff line change
@@ -681,6 +681,11 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
681681
"SiFive sf.cflush.d.l1 custom opcode table");
682682
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcease, DecoderTableXSfcease32,
683683
"SiFive sf.cease custom opcode table");
684+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXMIPSLSP, DecoderTableXmipslsp32,
685+
"MIPS mips.lsp custom opcode table");
686+
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXMIPSCMove,
687+
DecoderTableXmipscmove32,
688+
"MIPS mips.ccmov custom opcode table");
684689
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
685690
DecoderTableXCVbitmanip32,
686691
"CORE-V Bit Manipulation custom opcode table");

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

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Original file line numberDiff line numberDiff line change
@@ -308,6 +308,7 @@ enum OperandType : unsigned {
308308
OPERAND_UIMM6_LSB0,
309309
OPERAND_UIMM7,
310310
OPERAND_UIMM7_LSB00,
311+
OPERAND_UIMM7_LSB000,
311312
OPERAND_UIMM8_LSB00,
312313
OPERAND_UIMM8,
313314
OPERAND_UIMM8_LSB000,

‎llvm/lib/Target/RISCV/RISCV.h

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Original file line numberDiff line numberDiff line change
@@ -84,6 +84,8 @@ void initializeRISCVMoveMergePass(PassRegistry &);
8484

8585
FunctionPass *createRISCVPushPopOptimizationPass();
8686
void initializeRISCVPushPopOptPass(PassRegistry &);
87+
FunctionPass *createRISCVLoadStoreOptPass();
88+
void initializeRISCVLoadStoreOptPass(PassRegistry &);
8789

8890
FunctionPass *createRISCVZacasABIFixPass();
8991
void initializeRISCVZacasABIFixPass(PassRegistry &);

‎llvm/lib/Target/RISCV/RISCVFeatures.td

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Original file line numberDiff line numberDiff line change
@@ -1228,6 +1228,21 @@ def HasVendorXCVbi
12281228
: Predicate<"Subtarget->hasVendorXCVbi()">,
12291229
AssemblerPredicate<(all_of FeatureVendorXCVbi),
12301230
"'XCVbi' (CORE-V Immediate Branching)">;
1231+
// MIPS Extensions
1232+
1233+
def FeatureVendorXMIPSCMove
1234+
: RISCVExtension<1, 0, "MIPS conditional move instruction(s) (ccmov)">;
1235+
def HasVendorXMIPSCMove
1236+
: Predicate<"Subtarget->hasVendorXMIPSCMove()">,
1237+
AssemblerPredicate<(all_of FeatureVendorXMIPSCMove),
1238+
"'Xmipscmove' ('mips.ccmov' instruction)">;
1239+
def UseCCMovInsn : Predicate<"Subtarget->useCCMovInsn()">;
1240+
def FeatureVendorXMIPSLSP
1241+
: RISCVExtension<1, 0, "MIPS optimization for hardware load-store bonding">;
1242+
def HasVendorXMIPSLSP
1243+
: Predicate<"Subtarget->hasVendorXMIPSLSP()">,
1244+
AssemblerPredicate<(all_of FeatureVendorXMIPSLSP),
1245+
"'Xmipslsp' (load and store pair instructions)">;
12311246

12321247
// WCH / Nanjing Qinheng Microelectronics Extension(s)
12331248

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -409,7 +409,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
409409
setOperationAction(ISD::ABS, MVT::i32, Custom);
410410
}
411411

412-
if (!Subtarget.hasVendorXTHeadCondMov())
412+
if (Subtarget.useCCMovInsn())
413+
setOperationAction(ISD::SELECT, XLenVT, Legal);
414+
else if (!Subtarget.hasVendorXTHeadCondMov())
413415
setOperationAction(ISD::SELECT, XLenVT, Custom);
414416

415417
static const unsigned FPLegalNodeTypes[] = {

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

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Original file line numberDiff line numberDiff line change
@@ -2488,6 +2488,9 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
24882488
case RISCVOp::OPERAND_UIMM7_LSB00:
24892489
Ok = isShiftedUInt<5, 2>(Imm);
24902490
break;
2491+
case RISCVOp::OPERAND_UIMM7_LSB000:
2492+
Ok = isShiftedUInt<4, 3>(Imm);
2493+
break;
24912494
case RISCVOp::OPERAND_UIMM8_LSB00:
24922495
Ok = isShiftedUInt<6, 2>(Imm);
24932496
break;

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

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@@ -399,6 +399,10 @@ def ixlenimm_li_restricted : Operand<XLenVT> {
399399

400400
// Standalone (codegen-only) immleaf patterns.
401401

402+
// A 12-bit signed immediate plus one where the imm range will be -2047~2048.
403+
def simm12_plus1 : ImmLeaf<XLenVT,
404+
[{return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048;}]>;
405+
402406
// A 6-bit constant greater than 32.
403407
def uimm6gt32 : ImmLeaf<XLenVT, [{
404408
return isUInt<6>(Imm) && Imm > 32;
@@ -2133,6 +2137,7 @@ include "RISCVInstrInfoSFB.td"
21332137
include "RISCVInstrInfoXCV.td"
21342138
include "RISCVInstrInfoXwch.td"
21352139
include "RISCVInstrInfoXqci.td"
2140+
include "RISCVInstrInfoXMips.td"
21362141

21372142
//===----------------------------------------------------------------------===//
21382143
// Global ISel

‎llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td

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@@ -0,0 +1,169 @@
1+
//===-- RISCVInstrInfoXMips.td -----------------------------*- tablegen -*-===//
2+
//
3+
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
// See https://llvm.org/LICENSE.txt for license information.
5+
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
//
7+
//===----------------------------------------------------------------------===//
8+
//
9+
// This file describes the vendor extensions defined by MIPS.
10+
//
11+
//===----------------------------------------------------------------------===//
12+
13+
//===----------------------------------------------------------------------===//
14+
// Operand definitions.
15+
//===----------------------------------------------------------------------===//
16+
17+
// A 7-bit unsigned immediate where the least significant three bits are zero.
18+
def uimm7_lsb000 : RISCVOp,
19+
ImmLeaf<XLenVT, [{return isShiftedUInt<4, 3>(Imm);}]> {
20+
let ParserMatchClass = UImmAsmOperand<7, "Lsb000">;
21+
let EncoderMethod = "getImmOpValue";
22+
let DecoderMethod = "decodeUImmOperand<7>";
23+
let OperandType = "OPERAND_UIMM7_LSB000";
24+
let MCOperandPredicate = [{
25+
int64_t Imm;
26+
if (!MCOp.evaluateAsConstantImm(Imm))
27+
return false;
28+
return isShiftedUInt<4, 3>(Imm);
29+
}];
30+
}
31+
32+
//===----------------------------------------------------------------------===//
33+
// MIPS custom instruction formats
34+
//===----------------------------------------------------------------------===//
35+
36+
// Load double pair format.
37+
class LDPFormat<dag outs, dag ins, string opcodestr, string argstr>
38+
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
39+
bits<7> imm7;
40+
bits<5> rs1;
41+
bits<5> rd1;
42+
bits<5> rd2;
43+
44+
let Inst{31-27} = rd2;
45+
let Inst{26-23} = imm7{6-3};
46+
let Inst{22-20} = 0b000;
47+
let Inst{19-15} = rs1;
48+
let Inst{14-12} = 0b100;
49+
let Inst{11-7} = rd1;
50+
let Inst{6-0} = OPC_CUSTOM_0.Value;
51+
}
52+
53+
// Load word pair format.
54+
class LWPFormat<dag outs, dag ins, string opcodestr, string argstr>
55+
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
56+
bits<7> imm7;
57+
bits<5> rs1;
58+
bits<5> rd1;
59+
bits<5> rd2;
60+
61+
let Inst{31-27} = rd2;
62+
let Inst{26-22} = imm7{6-2};
63+
let Inst{21-20} = 0b01;
64+
let Inst{19-15} = rs1;
65+
let Inst{14-12} = 0b100;
66+
let Inst{11-7} = rd1;
67+
let Inst{6-0} = OPC_CUSTOM_0.Value;
68+
}
69+
70+
// Store double pair format.
71+
class SDPFormat<dag outs, dag ins, string opcodestr, string argstr>
72+
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
73+
bits<7> imm7;
74+
bits<5> rs3;
75+
bits<5> rs2;
76+
bits<5> rs1;
77+
78+
let Inst{31-27} = rs3;
79+
let Inst{26-25} = imm7{6-5};
80+
let Inst{24-20} = rs2;
81+
let Inst{19-15} = rs1;
82+
let Inst{14-12} = 0b101;
83+
let Inst{11-10} = imm7{4-3};
84+
let Inst{9-7} = 0b000;
85+
let Inst{6-0} = OPC_CUSTOM_0.Value;
86+
}
87+
88+
// Store word pair format.
89+
class SWPFormat<dag outs, dag ins, string opcodestr, string argstr>
90+
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
91+
bits<7> imm7;
92+
bits<5> rs3;
93+
bits<5> rs2;
94+
bits<5> rs1;
95+
96+
let Inst{31-27} = rs3;
97+
let Inst{26-25} = imm7{6-5};
98+
let Inst{24-20} = rs2;
99+
let Inst{19-15} = rs1;
100+
let Inst{14-12} = 0b101;
101+
let Inst{11-9} = imm7{4-2};
102+
let Inst{8-7} = 0b01;
103+
let Inst{6-0} = OPC_CUSTOM_0.Value;
104+
}
105+
106+
//===----------------------------------------------------------------------===//
107+
// MIPS extensions
108+
//===----------------------------------------------------------------------===//
109+
110+
let Predicates = [HasVendorXMIPSCMove], hasSideEffects = 0, mayLoad = 0, mayStore = 0,
111+
DecoderNamespace = "Xmipscmove" in {
112+
def CCMOV : RVInstR4<0b11, 0b011, OPC_CUSTOM_0, (outs GPR:$rd),
113+
(ins GPR:$rs1, GPR:$rs2, GPR:$rs3),
114+
"mips.ccmov", "$rd, $rs2, $rs1, $rs3">,
115+
Sched<[]>;
116+
}
117+
118+
let Predicates = [UseCCMovInsn] in {
119+
def : Pat<(select (XLenVT (setne (XLenVT GPR:$rs2), (XLenVT 0))),
120+
(XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
121+
(CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
122+
def : Pat<(select (XLenVT (setne (XLenVT GPR:$x), (XLenVT simm12_plus1:$y))),
123+
(XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
124+
(CCMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
125+
def : Pat<(select (XLenVT (setne (XLenVT GPR:$x), (XLenVT GPR:$y))),
126+
(XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
127+
(CCMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
128+
def : Pat<(select (XLenVT (seteq (XLenVT GPR:$rs2), (XLenVT 0))),
129+
(XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
130+
(CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
131+
def : Pat<(select (XLenVT (seteq (XLenVT GPR:$x), (XLenVT simm12_plus1:$y))),
132+
(XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
133+
(CCMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
134+
def : Pat<(select (XLenVT (seteq (XLenVT GPR:$x), (XLenVT GPR:$y))),
135+
(XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
136+
(CCMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
137+
def : Pat<(select (XLenVT GPR:$rs2), (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
138+
(CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
139+
}
140+
141+
let Predicates = [HasVendorXMIPSLSP], hasSideEffects = 0,
142+
DecoderNamespace = "Xmipslsp" in {
143+
144+
def LWP : LWPFormat<(outs GPR:$rd1, GPR:$rd2), (ins GPR:$rs1, uimm7_lsb00:$imm7),
145+
"mips.lwp", "$rd1, $rd2, ${imm7}(${rs1})">,
146+
Sched<[WriteLDW, WriteLDW, ReadMemBase]> {
147+
let mayLoad = 1;
148+
let mayStore = 0;
149+
}
150+
def LDP : LDPFormat<(outs GPR:$rd1, GPR:$rd2), (ins GPR:$rs1, uimm7_lsb000:$imm7),
151+
"mips.ldp", "$rd1, $rd2, ${imm7}(${rs1})">,
152+
Sched<[WriteLDD, WriteLDD, ReadMemBase]> {
153+
let mayLoad = 1;
154+
let mayStore = 0;
155+
}
156+
def SWP : SWPFormat<(outs), (ins GPR:$rs2, GPR:$rs3, GPR:$rs1, uimm7_lsb00:$imm7),
157+
"mips.swp", "$rs2, $rs3, ${imm7}(${rs1})">,
158+
Sched<[WriteSTW, ReadStoreData, ReadStoreData, ReadMemBase]> {
159+
let mayLoad = 0;
160+
let mayStore = 1;
161+
}
162+
def SDP : SDPFormat<(outs), (ins GPR:$rs2, GPR:$rs3, GPR:$rs1, uimm7_lsb000:$imm7),
163+
"mips.sdp", "$rs2, $rs3, ${imm7}(${rs1})">,
164+
Sched<[WriteSTD, ReadStoreData, ReadStoreData, ReadMemBase]> {
165+
let mayLoad = 0;
166+
let mayStore = 1;
167+
}
168+
169+
}

‎llvm/lib/Target/RISCV/RISCVProcessors.td

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -116,7 +116,9 @@ def MIPS_P8700 : RISCVProcessorModel<"mips-p8700",
116116
FeatureStdExtZba,
117117
FeatureStdExtZbb,
118118
FeatureStdExtZifencei,
119-
FeatureStdExtZicsr],
119+
FeatureStdExtZicsr,
120+
FeatureVendorXMIPSCMove,
121+
FeatureVendorXMIPSLSP],
120122
[TuneMIPSP8700]>;
121123

122124
def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32",

‎llvm/lib/Target/RISCV/RISCVSubtarget.cpp

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -62,6 +62,15 @@ static cl::opt<unsigned> RISCVMinimumJumpTableEntries(
6262
"riscv-min-jump-table-entries", cl::Hidden,
6363
cl::desc("Set minimum number of entries to use a jump table on RISCV"));
6464

65+
static cl::opt<bool>
66+
UseMIPSLoadStorePairsOpt("mips-riscv-load-store-pairs",
67+
cl::desc("RISCV: Optimize for load-store bonding"),
68+
cl::init(false), cl::Hidden);
69+
70+
static cl::opt<bool>
71+
UseCCMovInsn("riscv-ccmov", cl::desc("RISCV: Use 'mips.ccmov' instruction"),
72+
cl::init(true), cl::Hidden);
73+
6574
void RISCVSubtarget::anchor() {}
6675

6776
RISCVSubtarget &
@@ -238,3 +247,7 @@ void RISCVSubtarget::overridePostRASchedPolicy(MachineSchedPolicy &Policy,
238247
Policy.OnlyBottomUp = false;
239248
}
240249
}
250+
251+
bool RISCVSubtarget::useCCMovInsn() const {
252+
return UseCCMovInsn && HasVendorXMIPSCMove;
253+
}

‎llvm/lib/Target/RISCV/RISCVSubtarget.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -188,6 +188,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
188188
unsigned getXLen() const {
189189
return is64Bit() ? 64 : 32;
190190
}
191+
bool useLoadStorePairs() const;
192+
bool useCCMovInsn() const;
191193
unsigned getFLen() const {
192194
if (HasStdExtD)
193195
return 64;

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -389,6 +389,7 @@ class RISCVPassConfig : public TargetPassConfig {
389389
DAG->addMutation(createStoreClusterDAGMutation(
390390
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
391391
}
392+
392393
return DAG;
393394
}
394395

‎llvm/test/CodeGen/RISCV/select-and.ll

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,8 @@
33
; RUN: | FileCheck -check-prefix=RV32I %s
44
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
55
; RUN: | FileCheck -check-prefix=RV64I %s
6+
; RUN: llc -mtriple=riscv64 -mattr=+xmipscmove -verify-machineinstrs < %s \
7+
; RUN: | FileCheck -check-prefix=RV64I-CCMOV %s
68

79
;; There are a few different ways to lower (select (and A, B), X, Y). This test
810
;; ensures that we do so with as few branches as possible.
@@ -27,6 +29,12 @@ define signext i32 @select_of_and(i1 zeroext %a, i1 zeroext %b, i32 signext %c,
2729
; RV64I-NEXT: mv a0, a3
2830
; RV64I-NEXT: .LBB0_2:
2931
; RV64I-NEXT: ret
32+
;
33+
; RV64I-CCMOV-LABEL: select_of_and:
34+
; RV64I-CCMOV: # %bb.0:
35+
; RV64I-CCMOV-NEXT: and a0, a0, a1
36+
; RV64I-CCMOV-NEXT: mips.ccmov a0, a0, a2, a3
37+
; RV64I-CCMOV-NEXT: ret
3038
%1 = and i1 %a, %b
3139
%2 = select i1 %1, i32 %c, i32 %d
3240
ret i32 %2
@@ -69,6 +77,23 @@ define signext i32 @if_of_and(i1 zeroext %a, i1 zeroext %b) nounwind {
6977
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
7078
; RV64I-NEXT: addi sp, sp, 16
7179
; RV64I-NEXT: ret
80+
;
81+
; RV64I-CCMOV-LABEL: if_of_and:
82+
; RV64I-CCMOV: # %bb.0:
83+
; RV64I-CCMOV-NEXT: addi sp, sp, -16
84+
; RV64I-CCMOV-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
85+
; RV64I-CCMOV-NEXT: beqz a0, .LBB1_3
86+
; RV64I-CCMOV-NEXT: # %bb.1:
87+
; RV64I-CCMOV-NEXT: beqz a1, .LBB1_3
88+
; RV64I-CCMOV-NEXT: # %bb.2: # %if.then
89+
; RV64I-CCMOV-NEXT: call both
90+
; RV64I-CCMOV-NEXT: j .LBB1_4
91+
; RV64I-CCMOV-NEXT: .LBB1_3: # %if.else
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; RV64I-CCMOV-NEXT: call neither
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; RV64I-CCMOV-NEXT: .LBB1_4: # %if.end
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; RV64I-CCMOV-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64I-CCMOV-NEXT: addi sp, sp, 16
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; RV64I-CCMOV-NEXT: ret
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%1 = and i1 %a, %b
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br i1 %1, label %if.then, label %if.else
7499

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