@@ -94,6 +94,8 @@ def simm5nonzero : RISCVOp<XLenVT>,
94
94
95
95
def simm11 : RISCVSImmLeafOp<11>;
96
96
97
+ def simm16 : RISCVSImmOp<16>;
98
+
97
99
def simm16nonzero : RISCVOp<XLenVT>,
98
100
ImmLeaf<XLenVT, [{return (Imm != 0) && isInt<16>(Imm);}]> {
99
101
let ParserMatchClass = SImmAsmOperand<16, "NonZero">;
@@ -139,6 +141,219 @@ def simm32_lsb0 : Operand<OtherVT> {
139
141
// Instruction Formats
140
142
//===----------------------------------------------------------------------===//
141
143
144
+
145
+ class DirectiveInsnQC_EAI<dag outs, dag ins, string argstr>
146
+ : RVInst48<outs, ins, "", "", [], InstFormatQC_EAI> {
147
+ bits<7> opcode;
148
+ bits<3> func3;
149
+ bits<1> func1;
150
+
151
+ bits<5> rd;
152
+ bits<32> imm32;
153
+
154
+ let Inst{47-16} = imm32;
155
+ let Inst{15} = func1;
156
+ let Inst{14-12} = func3;
157
+ let Inst{11-7} = rd;
158
+ let Inst{6-0} = opcode;
159
+
160
+ let AsmString = ".insn qc.eai " # argstr;
161
+ }
162
+
163
+ class DirectiveInsnQC_EI<dag outs, dag ins, string argstr>
164
+ : RVInst48<outs, ins, "", "", [], InstFormatQC_EI> {
165
+ bits<7> opcode;
166
+ bits<3> func3;
167
+ bits<2> func2;
168
+
169
+ bits<5> rd;
170
+ bits<5> rs1;
171
+ bits<26> imm26;
172
+
173
+ let Inst{47-32} = imm26{25-10};
174
+ let Inst{31-30} = func2;
175
+ let Inst{29-20} = imm26{9-0};
176
+ let Inst{19-15} = rs1;
177
+ let Inst{14-12} = func3;
178
+ let Inst{11-7} = rd;
179
+ let Inst{6-0} = opcode;
180
+
181
+ let AsmString = ".insn qc.ei " # argstr;
182
+ }
183
+
184
+ class DirectiveInsnQC_EB<dag outs, dag ins, string argstr>
185
+ : RVInst48<outs, ins, "", "", [], InstFormatQC_EB> {
186
+ bits<7> opcode;
187
+ bits<3> func3;
188
+ bits<5> func5;
189
+
190
+ bits<5> rs1;
191
+ bits<12> imm12; // This one is the PC-relative offset
192
+ bits<16> imm16;
193
+
194
+ let Inst{47-32} = imm16;
195
+ let Inst{31} = imm12{11};
196
+ let Inst{30-25} = imm12{9-4};
197
+ let Inst{24-20} = func5;
198
+ let Inst{19-15} = rs1;
199
+ let Inst{14-12} = func3;
200
+ let Inst{11-8} = imm12{3-0};
201
+ let Inst{7} = imm12{10};
202
+ let Inst{6-0} = opcode;
203
+
204
+ let AsmString = ".insn qc.eb " # argstr;
205
+ }
206
+
207
+ class DirectiveInsnQC_EJ<dag outs, dag ins, string argstr>
208
+ : RVInst48<outs, ins, "", "", [], InstFormatQC_EJ> {
209
+ bits<7> opcode;
210
+ bits<3> func3;
211
+ bits<2> func2;
212
+ bits<5> func5;
213
+
214
+ bits<31> imm31;
215
+
216
+ let Inst{47-32} = imm31{30-15};
217
+ let Inst{31} = imm31{11};
218
+ let Inst{30-25} = imm31{9-4};
219
+ let Inst{24-20} = func5;
220
+ let Inst{19-17} = imm31{14-12};
221
+ let Inst{16-15} = func2;
222
+ let Inst{14-12} = func3;
223
+ let Inst{11-8} = imm31{3-0};
224
+ let Inst{7} = imm31{10};
225
+ let Inst{6-0} = opcode;
226
+
227
+ let AsmString = ".insn qc.ej " # argstr;
228
+ }
229
+
230
+ class DirectiveInsnQC_ES<dag outs, dag ins, string argstr>
231
+ : RVInst48<outs, ins, "", "", [], InstFormatQC_ES> {
232
+ bits<7> opcode;
233
+ bits<3> func3;
234
+ bits<2> func2;
235
+
236
+ bits<5> rs1;
237
+ bits<5> rs2;
238
+ bits<26> imm26;
239
+
240
+ let Inst{47-32} = imm26{25-10};
241
+ let Inst{31-30} = func2;
242
+ let Inst{29-25} = imm26{9-5};
243
+ let Inst{24-20} = rs2;
244
+ let Inst{19-15} = rs1;
245
+ let Inst{14-12} = func3;
246
+ let Inst{11-7} = imm26{4-0};
247
+ let Inst{6-0} = opcode;
248
+
249
+ let AsmString = ".insn qc.es " # argstr;
250
+ }
251
+
252
+
253
+ let isCodeGenOnly = true, hasSideEffects = true, mayLoad = true,
254
+ mayStore = true, hasNoSchedulingInfo = true, Predicates=[IsRV32] in {
255
+ def InsnQC_EAI : DirectiveInsnQC_EAI<(outs AnyReg:$rd),
256
+ (ins uimm7_opcode:$opcode,
257
+ uimm3:$func3,
258
+ uimm1:$func1,
259
+ simm32:$imm32),
260
+ "$opcode, $func3, $func1, $rd, $imm32">;
261
+ def InsnQC_EI : DirectiveInsnQC_EI<(outs AnyReg:$rd),
262
+ (ins uimm7_opcode:$opcode,
263
+ uimm3:$func3,
264
+ uimm2:$func2,
265
+ AnyReg:$rs1,
266
+ simm26:$imm26),
267
+ "$opcode, $func3, $func2, $rd, $rs1, $imm26">;
268
+ def InsnQC_EI_Mem : DirectiveInsnQC_EI<(outs AnyReg:$rd),
269
+ (ins uimm7_opcode:$opcode,
270
+ uimm3:$func3,
271
+ uimm2:$func2,
272
+ AnyReg:$rs1,
273
+ simm26:$imm26),
274
+ "$opcode, $func3, $func2, $rd, ${imm26}(${rs1})">;
275
+ def InsnQC_EB : DirectiveInsnQC_EB<(outs),
276
+ (ins uimm7_opcode:$opcode,
277
+ uimm3:$func3,
278
+ uimm5:$func5,
279
+ AnyReg:$rs1,
280
+ simm16:$imm16,
281
+ simm13_lsb0:$imm12),
282
+ "$opcode, $func3, $func5, $rs1, $imm16, $imm12">;
283
+ def InsnQC_EJ : DirectiveInsnQC_EJ<(outs),
284
+ (ins uimm7_opcode:$opcode,
285
+ uimm3:$func3,
286
+ uimm2:$func2,
287
+ uimm5:$func5,
288
+ simm32_lsb0:$imm31),
289
+ "$opcode, $func3, $func2, $func5, $imm31">;
290
+ def InsnQC_ES : DirectiveInsnQC_ES<(outs),
291
+ (ins uimm7_opcode:$opcode,
292
+ uimm3:$func3,
293
+ uimm2:$func2,
294
+ AnyReg:$rs2,
295
+ AnyReg:$rs1,
296
+ simm26:$imm26),
297
+ "$opcode, $func3, $func2, $rs2, ${imm26}(${rs1})">;
298
+ } // isCodeGenOnly, hasSideEffects, mayLoad, mayStore, hasNoSchedulingInfo, Predicates
299
+
300
+ let EmitPriority = 0, Predicates = [IsRV32] in {
301
+ def : InstAlias<".insn_qc.eai $opcode, $func3, $func1, $rd, $imm32",
302
+ (InsnQC_EAI AnyReg:$rd,
303
+ uimm7_opcode:$opcode,
304
+ uimm3:$func3,
305
+ uimm1:$func1,
306
+ simm32:$imm32)>;
307
+ def : InstAlias<".insn_qc.ei $opcode, $func3, $func2, $rd, $rs1, $imm26",
308
+ (InsnQC_EI AnyReg:$rd,
309
+ uimm7_opcode:$opcode,
310
+ uimm3:$func3,
311
+ uimm2:$func2,
312
+ AnyReg:$rs1,
313
+ simm26:$imm26)>;
314
+ def : InstAlias<".insn_qc.ei $opcode, $func3, $func2, $rd, ${imm26}(${rs1})",
315
+ (InsnQC_EI_Mem AnyReg:$rd,
316
+ uimm7_opcode:$opcode,
317
+ uimm3:$func3,
318
+ uimm2:$func2,
319
+ AnyReg:$rs1,
320
+ simm26:$imm26)>;
321
+ def : InstAlias<".insn_qc.ei $opcode, $func3, $func2, $rd, (${rs1})",
322
+ (InsnQC_EI_Mem AnyReg:$rd,
323
+ uimm7_opcode:$opcode,
324
+ uimm3:$func3,
325
+ uimm2:$func2,
326
+ AnyReg:$rs1,
327
+ 0)>;
328
+ def : InstAlias<".insn_qc.eb $opcode, $func3, $func5, $rs1, $imm16, $imm12",
329
+ (InsnQC_EB uimm7_opcode:$opcode,
330
+ uimm3:$func3,
331
+ uimm5:$func5,
332
+ AnyReg:$rs1,
333
+ simm16:$imm16,
334
+ simm13_lsb0:$imm12)>;
335
+ def : InstAlias<".insn_qc.ej $opcode, $func3, $func2, $func5, $imm31",
336
+ (InsnQC_EJ uimm7_opcode:$opcode,
337
+ uimm3:$func3,
338
+ uimm2:$func2,
339
+ uimm5:$func5,
340
+ simm32_lsb0:$imm31)>;
341
+ def : InstAlias<".insn_qc.es $opcode, $func3, $func2, $rs2, ${imm26}(${rs1})",
342
+ (InsnQC_ES uimm7_opcode:$opcode,
343
+ uimm3:$func3,
344
+ uimm2:$func2,
345
+ AnyReg:$rs2,
346
+ AnyReg:$rs1,
347
+ simm26:$imm26)>;
348
+ def : InstAlias<".insn_qc.es $opcode, $func3, $func2, $rs2, (${rs1})",
349
+ (InsnQC_ES uimm7_opcode:$opcode,
350
+ uimm3:$func3,
351
+ uimm2:$func2,
352
+ AnyReg:$rs2,
353
+ AnyReg:$rs1,
354
+ 0)>;
355
+ } // EmitPriority = 0, Predicates = [IsRV32]
356
+
142
357
//===----------------------------------------------------------------------===//
143
358
// Instruction Class Templates
144
359
//===----------------------------------------------------------------------===//
0 commit comments