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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 |
| 2 | +; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu -mcpu=cascadelake < %s | FileCheck %s |
| 3 | + |
| 4 | +define void @test(ptr %0, i32 %add651) { |
| 5 | +; CHECK-LABEL: define void @test( |
| 6 | +; CHECK-SAME: ptr [[TMP0:%.*]], i32 [[ADD651:%.*]]) #[[ATTR0:[0-9]+]] { |
| 7 | +; CHECK-NEXT: [[ENTRY:.*:]] |
| 8 | +; CHECK-NEXT: [[PREDPEL11:%.*]] = alloca [0 x [0 x [25 x i32]]], i32 0, align 16 |
| 9 | +; CHECK-NEXT: [[ARRAYIDX469_6:%.*]] = getelementptr i8, ptr [[PREDPEL11]], i64 28 |
| 10 | +; CHECK-NEXT: [[ARRAYIDX469_7:%.*]] = getelementptr i8, ptr [[PREDPEL11]], i64 32 |
| 11 | +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[PREDPEL11]], i64 36 |
| 12 | +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX469_7]], align 16 |
| 13 | +; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i32>, ptr [[ARRAYIDX469_6]], align 4 |
| 14 | +; CHECK-NEXT: [[CONV470_7:%.*]] = trunc i32 [[TMP2]] to i16 |
| 15 | +; CHECK-NEXT: store i16 [[CONV470_7]], ptr [[TMP0]], align 2 |
| 16 | +; CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP0]], align 8 |
| 17 | +; CHECK-NEXT: [[ARRAYIDX660:%.*]] = getelementptr i8, ptr [[TMP4]], i64 7800 |
| 18 | +; CHECK-NEXT: [[ARRAYIDX689:%.*]] = getelementptr i8, ptr [[TMP4]], i64 7816 |
| 19 | +; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i32>, ptr [[TMP1]], align 4 |
| 20 | +; CHECK-NEXT: [[TMP6:%.*]] = add <2 x i32> [[TMP3]], <i32 1, i32 1> |
| 21 | +; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> [[TMP5]], <2 x i32> <i32 1, i32 2> |
| 22 | +; CHECK-NEXT: [[TMP8:%.*]] = add <2 x i32> [[TMP6]], [[TMP7]] |
| 23 | +; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x i32> [[TMP5]], <2 x i32> <i32 1, i32 poison>, <2 x i32> <i32 2, i32 1> |
| 24 | +; CHECK-NEXT: [[TMP10:%.*]] = add <2 x i32> [[TMP8]], [[TMP9]] |
| 25 | +; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> poison, i32 [[ADD651]], i32 0 |
| 26 | +; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> |
| 27 | +; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <4 x i32> [[TMP11]], <4 x i32> [[TMP12]], <4 x i32> <i32 0, i32 5, i32 poison, i32 poison> |
| 28 | +; CHECK-NEXT: [[TMP14:%.*]] = call <4 x i32> @llvm.vector.insert.v4i32.v2i32(<4 x i32> [[TMP13]], <2 x i32> [[TMP10]], i64 2) |
| 29 | +; CHECK-NEXT: [[TMP15:%.*]] = lshr <4 x i32> [[TMP14]], <i32 1, i32 1, i32 1, i32 1> |
| 30 | +; CHECK-NEXT: [[TMP16:%.*]] = trunc <4 x i32> [[TMP15]] to <4 x i16> |
| 31 | +; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <4 x i16> [[TMP16]], <4 x i16> poison, <2 x i32> <i32 1, i32 2> |
| 32 | +; CHECK-NEXT: store <2 x i16> [[TMP17]], ptr [[ARRAYIDX689]], align 8 |
| 33 | +; CHECK-NEXT: [[TMP18:%.*]] = extractelement <4 x i16> [[TMP16]], i32 3 |
| 34 | +; CHECK-NEXT: store i16 [[TMP18]], ptr [[TMP4]], align 8 |
| 35 | +; CHECK-NEXT: store <4 x i16> [[TMP16]], ptr [[ARRAYIDX660]], align 8 |
| 36 | +; CHECK-NEXT: ret void |
| 37 | +; |
| 38 | +entry: |
| 39 | + %PredPel11 = alloca [0 x [0 x [25 x i32]]], i32 0, align 16 |
| 40 | + %arrayidx469.6 = getelementptr i8, ptr %PredPel11, i64 28 |
| 41 | + %1 = load i32, ptr %arrayidx469.6, align 4 |
| 42 | + %arrayidx469.7 = getelementptr i8, ptr %PredPel11, i64 32 |
| 43 | + %2 = load i32, ptr %arrayidx469.7, align 16 |
| 44 | + %conv470.7 = trunc i32 %2 to i16 |
| 45 | + store i16 %conv470.7, ptr %0, align 2 |
| 46 | + %3 = getelementptr i8, ptr %PredPel11, i64 36 |
| 47 | + %4 = getelementptr i8, ptr %PredPel11, i64 40 |
| 48 | + %5 = load ptr, ptr %0, align 8 |
| 49 | + %add6511 = add i32 %1, 1 |
| 50 | + %shr656 = lshr i32 %add651, 1 |
| 51 | + %conv657 = trunc i32 %shr656 to i16 |
| 52 | + %arrayidx660 = getelementptr i8, ptr %5, i64 7800 |
| 53 | + store i16 %conv657, ptr %arrayidx660, align 8 |
| 54 | + %shr685 = lshr i32 %2, 1 |
| 55 | + %conv686 = trunc i32 %shr685 to i16 |
| 56 | + %arrayidx689 = getelementptr i8, ptr %5, i64 7816 |
| 57 | + store i16 %conv686, ptr %arrayidx689, align 8 |
| 58 | + %arrayidx694 = getelementptr i8, ptr %5, i64 7802 |
| 59 | + store i16 %conv686, ptr %arrayidx694, align 2 |
| 60 | + %6 = load i32, ptr %3, align 4 |
| 61 | + %add716 = add i32 %add6511, %2 |
| 62 | + %add717 = add i32 %add716, 1 |
| 63 | + %shr718 = lshr i32 %add717, 1 |
| 64 | + %conv719 = trunc i32 %shr718 to i16 |
| 65 | + %arrayidx727 = getelementptr i8, ptr %5, i64 7818 |
| 66 | + store i16 %conv719, ptr %arrayidx727, align 2 |
| 67 | + %arrayidx731 = getelementptr i8, ptr %5, i64 7804 |
| 68 | + store i16 %conv719, ptr %arrayidx731, align 4 |
| 69 | + %7 = load i32, ptr %4, align 8 |
| 70 | + %add750 = add i32 %2, 1 |
| 71 | + %add753 = add i32 %add750, %6 |
| 72 | + %add754 = add i32 %add753, %7 |
| 73 | + %shr755 = lshr i32 %add754, 1 |
| 74 | + %conv756 = trunc i32 %shr755 to i16 |
| 75 | + store i16 %conv756, ptr %5, align 8 |
| 76 | + %arrayidx772 = getelementptr i8, ptr %5, i64 7806 |
| 77 | + store i16 %conv756, ptr %arrayidx772, align 2 |
| 78 | + ret void |
| 79 | +} |
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