Skip to content

Commit 0ed129d

Browse files
srpandearsenm
authored andcommitted
AMDGPU: Add codegen support for gfx950 v_ashr_pk_i8/u8_i32
Co-authored-by: Sirish Pande <[email protected]>
1 parent 410d5e1 commit 0ed129d

File tree

2 files changed

+72
-0
lines changed

2 files changed

+72
-0
lines changed

llvm/lib/Target/AMDGPU/VOP3Instructions.td

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1453,6 +1453,23 @@ let SubtargetPredicate = HasAshrPkInsts, isReMaterializable = 1 in {
14531453
defm V_ASHR_PK_U8_I32 : VOP3Inst<"v_ashr_pk_u8_i32", VOP3_Profile<VOP_I16_I32_I32_I32, VOP3_OPSEL_ONLY>, int_amdgcn_ashr_pk_u8_i32>;
14541454
} // End SubtargetPredicate = HasAshrPkInsts, isReMaterializable = 1
14551455

1456+
class AshrPkI8Pat<VOP3_Pseudo inst, int lo, int hi>: GCNPat<
1457+
(i16 (or (i16 (shl (i16 (trunc (i32 (AMDGPUsmed3 (i32 (sra i32:$src1, i32:$src2)), (i32 lo), (i32 hi))))), (i16 8))),
1458+
(i16 (and (i16 (trunc (i32 (AMDGPUsmed3 (i32 (sra i32:$src0, i32:$src2)), (i32 lo), (i32 hi))))), (i16 255))))),
1459+
(inst 0, VSrc_b32:$src0, 0, VSrc_b32:$src1, 0, VSrc_b32:$src2, 0 )
1460+
>;
1461+
1462+
class AshrPkU8Pat<VOP3_Pseudo inst, int lo, int hi>: GCNPat<
1463+
(i16 (or (i16 (shl (i16 (trunc (i32 (AMDGPUsmed3 (i32 (sra i32:$src1, i32:$src2)), (i32 lo), (i32 hi))))), (i16 8))),
1464+
(i16 (trunc (i32 (AMDGPUsmed3 (i32 (sra i32:$src0, i32:$src2)), (i32 lo), (i32 hi))))))),
1465+
(inst 0, VSrc_b32:$src0, 0, VSrc_b32:$src1, 0, VSrc_b32:$src2, 0 )
1466+
>;
1467+
1468+
let SubtargetPredicate = HasAshrPkInsts in {
1469+
def : AshrPkI8Pat<V_ASHR_PK_I8_I32_e64, -128, 127>;
1470+
def : AshrPkU8Pat<V_ASHR_PK_U8_I32_e64, 0, 255>;
1471+
}
1472+
14561473
//===----------------------------------------------------------------------===//
14571474
// Integer Clamp Patterns
14581475
//===----------------------------------------------------------------------===//

llvm/test/CodeGen/AMDGPU/v_ashr_pk.ll

Lines changed: 55 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,55 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2+
; RUN: llc -mtriple=amdgcn -mcpu=gfx950 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX950 %s
3+
define amdgpu_kernel void @v_ashr_pk_i8_i32(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) #0 {
4+
; GFX950-LABEL: v_ashr_pk_i8_i32:
5+
; GFX950: ; %bb.0:
6+
; GFX950-NEXT: s_load_dword s2, s[0:1], 0x34
7+
; GFX950-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
8+
; GFX950-NEXT: v_mov_b32_e32 v0, 0
9+
; GFX950-NEXT: s_waitcnt lgkmcnt(0)
10+
; GFX950-NEXT: s_and_b32 s0, s2, 31
11+
; GFX950-NEXT: v_mov_b32_e32 v1, s7
12+
; GFX950-NEXT: v_mov_b32_e32 v2, s0
13+
; GFX950-NEXT: v_ashr_pk_i8_i32 v1, s6, v1, v2
14+
; GFX950-NEXT: global_store_short v0, v1, s[4:5]
15+
; GFX950-NEXT: s_endpgm
16+
%insert.0 = insertelement <2 x i32> poison, i32 %src0, i64 0
17+
%build_vector = insertelement <2 x i32> %insert.0, i32 %src1, i64 1
18+
%src2.clamp = and i32 %src2, 31
19+
%insert.1 = insertelement <2 x i32> poison, i32 %src2.clamp, i64 0
20+
%src2.broadcast = shufflevector <2 x i32> %insert.1, <2 x i32> poison, <2 x i32> zeroinitializer
21+
%ashr = ashr <2 x i32> %build_vector, %src2.broadcast
22+
%sat.low = tail call <2 x i32> @llvm.smax.v2i32(<2 x i32> %ashr, <2 x i32> <i32 -128, i32 -128>)
23+
%sat.hi = tail call <2 x i32> @llvm.smin.v2i32(<2 x i32> %sat.low, <2 x i32> <i32 127, i32 127>)
24+
%trunc = trunc nsw <2 x i32> %sat.hi to <2 x i8>
25+
%ret = bitcast <2 x i8> %trunc to i16
26+
store i16 %ret, ptr addrspace(1) %out
27+
ret void
28+
}
29+
30+
define amdgpu_kernel void @v_ashr_pk_u8_i32(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) #0 {
31+
; GFX950-LABEL: v_ashr_pk_u8_i32:
32+
; GFX950: ; %bb.0:
33+
; GFX950-NEXT: s_load_dword s2, s[0:1], 0x34
34+
; GFX950-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
35+
; GFX950-NEXT: v_mov_b32_e32 v0, 0
36+
; GFX950-NEXT: s_waitcnt lgkmcnt(0)
37+
; GFX950-NEXT: s_and_b32 s0, s2, 31
38+
; GFX950-NEXT: v_mov_b32_e32 v1, s7
39+
; GFX950-NEXT: v_mov_b32_e32 v2, s0
40+
; GFX950-NEXT: v_ashr_pk_u8_i32 v1, s6, v1, v2
41+
; GFX950-NEXT: global_store_short v0, v1, s[4:5]
42+
; GFX950-NEXT: s_endpgm
43+
%insert.0 = insertelement <2 x i32> poison, i32 %src0, i64 0
44+
%build_vector = insertelement <2 x i32> %insert.0, i32 %src1, i64 1
45+
%src2.clamp = and i32 %src2, 31
46+
%insert.1 = insertelement <2 x i32> poison, i32 %src2.clamp, i64 0
47+
%src2.broadcast = shufflevector <2 x i32> %insert.1, <2 x i32> poison, <2 x i32> zeroinitializer
48+
%ashr = ashr <2 x i32> %build_vector, %src2.broadcast
49+
%sat.low = tail call <2 x i32> @llvm.smax.v2i32(<2 x i32> %ashr, <2 x i32> <i32 0, i32 0>)
50+
%sat.hi = tail call <2 x i32> @llvm.smin.v2i32(<2 x i32> %sat.low, <2 x i32> <i32 255, i32 255>)
51+
%trunc = trunc nsw <2 x i32> %sat.hi to <2 x i8>
52+
%ret = bitcast <2 x i8> %trunc to i16
53+
store i16 %ret, ptr addrspace(1) %out
54+
ret void
55+
}

0 commit comments

Comments
 (0)