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1 parent d3ec8c2 commit 0ef61edCopy full SHA for 0ef61ed
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -13490,6 +13490,7 @@ struct NodeExtensionHelper {
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MVT NarrowVT = getNarrowType(Root, *SupportsExt);
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SDValue Source = getSource();
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+ assert(Subtarget.getTargetLowering()->isTypeLegal(Source.getValueType()));
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if (Source.getValueType() == NarrowVT)
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return Source;
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@@ -13657,9 +13658,6 @@ struct NodeExtensionHelper {
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unsigned ScalarBits = VT.getScalarSizeInBits();
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unsigned NarrowScalarBits = NarrowVT.getScalarSizeInBits();
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- assert(
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- Subtarget.getTargetLowering()->isTypeLegal(NarrowElt.getValueType()));
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-
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// Ensure the extension's semantic is equivalent to rvv vzext or vsext.
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if (ScalarBits != NarrowScalarBits * 2)
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break;
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