@@ -417,18 +417,26 @@ define <32 x i8> @test_buildvector_v32i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4,
417
417
define <4 x double > @test_buildvector_4f64_2_var (double %a0 , double %a1 ) {
418
418
; AVX-32-LABEL: test_buildvector_4f64_2_var:
419
419
; AVX-32: # %bb.0:
420
- ; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %xmm0
421
- ; AVX-32-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
422
- ; AVX-32-NEXT: vmovhps {{.*#+}} xmm1 = xmm1[0,1],mem[0,1]
423
- ; AVX-32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
420
+ ; AVX-32-NEXT: vbroadcastsd {{[0-9]+}}(%esp), %ymm0
421
+ ; AVX-32-NEXT: vbroadcastsd {{[0-9]+}}(%esp), %ymm1
422
+ ; AVX-32-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3,4,5],ymm1[6,7]
424
423
; AVX-32-NEXT: retl
425
424
;
426
- ; AVX-64-LABEL: test_buildvector_4f64_2_var:
427
- ; AVX-64: # %bb.0:
428
- ; AVX-64-NEXT: vmovlhps {{.*#+}} xmm2 = xmm1[0],xmm0[0]
429
- ; AVX-64-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
430
- ; AVX-64-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
431
- ; AVX-64-NEXT: retq
425
+ ; AVX1-64-LABEL: test_buildvector_4f64_2_var:
426
+ ; AVX1-64: # %bb.0:
427
+ ; AVX1-64-NEXT: vmovddup {{.*#+}} xmm1 = xmm1[0,0]
428
+ ; AVX1-64-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1
429
+ ; AVX1-64-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
430
+ ; AVX1-64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
431
+ ; AVX1-64-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5],ymm0[6,7]
432
+ ; AVX1-64-NEXT: retq
433
+ ;
434
+ ; AVX2-64-LABEL: test_buildvector_4f64_2_var:
435
+ ; AVX2-64: # %bb.0:
436
+ ; AVX2-64-NEXT: vbroadcastsd %xmm1, %ymm1
437
+ ; AVX2-64-NEXT: vbroadcastsd %xmm0, %ymm0
438
+ ; AVX2-64-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5],ymm0[6,7]
439
+ ; AVX2-64-NEXT: retq
432
440
%v0 = insertelement <4 x double > poison, double %a0 , i32 0
433
441
%v1 = insertelement <4 x double > %v0 , double %a1 , i32 1
434
442
%v2 = insertelement <4 x double > %v1 , double %a1 , i32 2
@@ -441,20 +449,16 @@ define <4 x double> @test_buildvector_4f64_2_load(ptr %p0, ptr %p1) {
441
449
; AVX-32: # %bb.0:
442
450
; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %eax
443
451
; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
444
- ; AVX-32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
445
- ; AVX-32-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
446
- ; AVX-32-NEXT: vmovlhps {{.*#+}} xmm2 = xmm1[0],xmm0[0]
447
- ; AVX-32-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
448
- ; AVX-32-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
452
+ ; AVX-32-NEXT: vbroadcastsd (%ecx), %ymm0
453
+ ; AVX-32-NEXT: vbroadcastsd (%eax), %ymm1
454
+ ; AVX-32-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3,4,5],ymm1[6,7]
449
455
; AVX-32-NEXT: retl
450
456
;
451
457
; AVX-64-LABEL: test_buildvector_4f64_2_load:
452
458
; AVX-64: # %bb.0:
453
- ; AVX-64-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
454
- ; AVX-64-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
455
- ; AVX-64-NEXT: vmovlhps {{.*#+}} xmm2 = xmm1[0],xmm0[0]
456
- ; AVX-64-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
457
- ; AVX-64-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
459
+ ; AVX-64-NEXT: vbroadcastsd (%rsi), %ymm0
460
+ ; AVX-64-NEXT: vbroadcastsd (%rdi), %ymm1
461
+ ; AVX-64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3,4,5],ymm1[6,7]
458
462
; AVX-64-NEXT: retq
459
463
%a0 = load double , ptr %p0
460
464
%a1 = load double , ptr %p1
0 commit comments