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[PowerPC][NFC] Added tests for prologue and epilogue code gen.
Added four test files to check the existing behaviour of prologue and epilogue code generation. This patch was done as a setup for the upcoming patch listed on Phabricator that will change how the prologue and epilogue work. The upcoming patch is: https://reviews.llvm.org/D42590 llvm-svn: 353994
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‎llvm/test/CodeGen/PowerPC/CSR-fit.ll

Lines changed: 280 additions & 0 deletions
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=CHECK-PWR8 %s
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; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=CHECK-PWR9 %s
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declare signext i32 @callee(i32 signext) local_unnamed_addr
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define dso_local signext i32 @caller1(i32 signext %a, i32 signext %b) local_unnamed_addr {
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; CHECK-PWR8-LABEL: caller1:
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; CHECK-PWR8: # %bb.0: # %entry
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; CHECK-PWR8-NEXT: mflr r0
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; CHECK-PWR8-NEXT: std r0, 16(r1)
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; CHECK-PWR8-NEXT: stdu r1, -176(r1)
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; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 176
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; CHECK-PWR8-NEXT: .cfi_offset lr, 16
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; CHECK-PWR8-NEXT: .cfi_offset r14, -144
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; CHECK-PWR8-NEXT: .cfi_offset r15, -136
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; CHECK-PWR8-NEXT: std r14, 32(r1) # 8-byte Folded Spill
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; CHECK-PWR8-NEXT: std r15, 40(r1) # 8-byte Folded Spill
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; CHECK-PWR8-NEXT: #APP
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; CHECK-PWR8-NEXT: add r3, r3, r4
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; CHECK-PWR8-NEXT: #NO_APP
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; CHECK-PWR8-NEXT: extsw r3, r3
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; CHECK-PWR8-NEXT: bl callee
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; CHECK-PWR8-NEXT: nop
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; CHECK-PWR8-NEXT: ld r15, 40(r1) # 8-byte Folded Reload
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; CHECK-PWR8-NEXT: ld r14, 32(r1) # 8-byte Folded Reload
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; CHECK-PWR8-NEXT: addi r1, r1, 176
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; CHECK-PWR8-NEXT: ld r0, 16(r1)
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; CHECK-PWR8-NEXT: mtlr r0
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; CHECK-PWR8-NEXT: blr
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;
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; CHECK-PWR9-LABEL: caller1:
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; CHECK-PWR9: # %bb.0: # %entry
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; CHECK-PWR9-NEXT: mflr r0
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; CHECK-PWR9-NEXT: std r0, 16(r1)
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; CHECK-PWR9-NEXT: stdu r1, -176(r1)
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; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 176
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; CHECK-PWR9-NEXT: .cfi_offset lr, 16
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; CHECK-PWR9-NEXT: .cfi_offset r14, -144
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; CHECK-PWR9-NEXT: .cfi_offset r15, -136
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; CHECK-PWR9-NEXT: std r14, 32(r1) # 8-byte Folded Spill
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; CHECK-PWR9-NEXT: std r15, 40(r1) # 8-byte Folded Spill
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; CHECK-PWR9-NEXT: #APP
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; CHECK-PWR9-NEXT: add r3, r3, r4
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; CHECK-PWR9-NEXT: #NO_APP
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; CHECK-PWR9-NEXT: extsw r3, r3
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; CHECK-PWR9-NEXT: bl callee
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; CHECK-PWR9-NEXT: nop
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; CHECK-PWR9-NEXT: ld r15, 40(r1) # 8-byte Folded Reload
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; CHECK-PWR9-NEXT: ld r14, 32(r1) # 8-byte Folded Reload
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; CHECK-PWR9-NEXT: addi r1, r1, 176
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; CHECK-PWR9-NEXT: ld r0, 16(r1)
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; CHECK-PWR9-NEXT: mtlr r0
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; CHECK-PWR9-NEXT: blr
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entry:
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%0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{r15}"(i32 %a, i32 %b)
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%call = tail call signext i32 @callee(i32 signext %0)
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ret i32 %call
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}
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define dso_local signext i32 @caller2(i32 signext %a, i32 signext %b) local_unnamed_addr {
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; CHECK-PWR8-LABEL: caller2:
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; CHECK-PWR8: # %bb.0: # %entry
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; CHECK-PWR8-NEXT: mflr r0
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; CHECK-PWR8-NEXT: std r0, 16(r1)
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; CHECK-PWR8-NEXT: stdu r1, -176(r1)
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; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 176
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; CHECK-PWR8-NEXT: .cfi_offset lr, 16
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; CHECK-PWR8-NEXT: .cfi_offset f14, -144
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; CHECK-PWR8-NEXT: .cfi_offset f15, -136
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; CHECK-PWR8-NEXT: stfd f14, 32(r1) # 8-byte Folded Spill
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; CHECK-PWR8-NEXT: stfd f15, 40(r1) # 8-byte Folded Spill
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; CHECK-PWR8-NEXT: #APP
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; CHECK-PWR8-NEXT: add r3, r3, r4
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; CHECK-PWR8-NEXT: #NO_APP
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; CHECK-PWR8-NEXT: extsw r3, r3
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; CHECK-PWR8-NEXT: bl callee
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; CHECK-PWR8-NEXT: nop
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; CHECK-PWR8-NEXT: lfd f15, 40(r1) # 8-byte Folded Reload
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; CHECK-PWR8-NEXT: lfd f14, 32(r1) # 8-byte Folded Reload
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; CHECK-PWR8-NEXT: addi r1, r1, 176
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; CHECK-PWR8-NEXT: ld r0, 16(r1)
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; CHECK-PWR8-NEXT: mtlr r0
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; CHECK-PWR8-NEXT: blr
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;
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; CHECK-PWR9-LABEL: caller2:
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; CHECK-PWR9: # %bb.0: # %entry
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; CHECK-PWR9-NEXT: mflr r0
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; CHECK-PWR9-NEXT: std r0, 16(r1)
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; CHECK-PWR9-NEXT: stdu r1, -176(r1)
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; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 176
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; CHECK-PWR9-NEXT: .cfi_offset lr, 16
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; CHECK-PWR9-NEXT: .cfi_offset f14, -144
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; CHECK-PWR9-NEXT: .cfi_offset f15, -136
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; CHECK-PWR9-NEXT: stfd f14, 32(r1) # 8-byte Folded Spill
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; CHECK-PWR9-NEXT: stfd f15, 40(r1) # 8-byte Folded Spill
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; CHECK-PWR9-NEXT: #APP
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; CHECK-PWR9-NEXT: add r3, r3, r4
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; CHECK-PWR9-NEXT: #NO_APP
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; CHECK-PWR9-NEXT: extsw r3, r3
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; CHECK-PWR9-NEXT: bl callee
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; CHECK-PWR9-NEXT: nop
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; CHECK-PWR9-NEXT: lfd f15, 40(r1) # 8-byte Folded Reload
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; CHECK-PWR9-NEXT: lfd f14, 32(r1) # 8-byte Folded Reload
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; CHECK-PWR9-NEXT: addi r1, r1, 176
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; CHECK-PWR9-NEXT: ld r0, 16(r1)
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; CHECK-PWR9-NEXT: mtlr r0
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; CHECK-PWR9-NEXT: blr
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entry:
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%0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{f14},~{f15}"(i32 %a, i32 %b)
114+
%call = tail call signext i32 @callee(i32 signext %0)
115+
ret i32 %call
116+
}
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define dso_local signext i32 @caller3(i32 signext %a, i32 signext %b) local_unnamed_addr {
119+
; CHECK-PWR8-LABEL: caller3:
120+
; CHECK-PWR8: # %bb.0: # %entry
121+
; CHECK-PWR8-NEXT: mflr r0
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; CHECK-PWR8-NEXT: std r0, 16(r1)
123+
; CHECK-PWR8-NEXT: stdu r1, -240(r1)
124+
; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 240
125+
; CHECK-PWR8-NEXT: .cfi_offset lr, 16
126+
; CHECK-PWR8-NEXT: .cfi_offset v20, -192
127+
; CHECK-PWR8-NEXT: .cfi_offset v21, -176
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; CHECK-PWR8-NEXT: li r5, 48
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; CHECK-PWR8-NEXT: stxvd2x v20, r1, r5 # 16-byte Folded Spill
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; CHECK-PWR8-NEXT: li r5, 64
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; CHECK-PWR8-NEXT: stxvd2x v21, r1, r5 # 16-byte Folded Spill
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; CHECK-PWR8-NEXT: #APP
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; CHECK-PWR8-NEXT: add r3, r3, r4
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; CHECK-PWR8-NEXT: #NO_APP
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; CHECK-PWR8-NEXT: extsw r3, r3
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; CHECK-PWR8-NEXT: bl callee
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; CHECK-PWR8-NEXT: nop
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; CHECK-PWR8-NEXT: li r4, 64
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; CHECK-PWR8-NEXT: lxvd2x v21, r1, r4 # 16-byte Folded Reload
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; CHECK-PWR8-NEXT: li r4, 48
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; CHECK-PWR8-NEXT: lxvd2x v20, r1, r4 # 16-byte Folded Reload
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; CHECK-PWR8-NEXT: addi r1, r1, 240
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; CHECK-PWR8-NEXT: ld r0, 16(r1)
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; CHECK-PWR8-NEXT: mtlr r0
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; CHECK-PWR8-NEXT: blr
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;
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; CHECK-PWR9-LABEL: caller3:
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; CHECK-PWR9: # %bb.0: # %entry
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; CHECK-PWR9-NEXT: mflr r0
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; CHECK-PWR9-NEXT: std r0, 16(r1)
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; CHECK-PWR9-NEXT: stdu r1, -224(r1)
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; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 224
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; CHECK-PWR9-NEXT: .cfi_offset lr, 16
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; CHECK-PWR9-NEXT: .cfi_offset v20, -192
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; CHECK-PWR9-NEXT: .cfi_offset v21, -176
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; CHECK-PWR9-NEXT: stxv v20, 32(r1) # 16-byte Folded Spill
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; CHECK-PWR9-NEXT: stxv v21, 48(r1) # 16-byte Folded Spill
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; CHECK-PWR9-NEXT: #APP
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; CHECK-PWR9-NEXT: add r3, r3, r4
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; CHECK-PWR9-NEXT: #NO_APP
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; CHECK-PWR9-NEXT: extsw r3, r3
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; CHECK-PWR9-NEXT: bl callee
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; CHECK-PWR9-NEXT: nop
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; CHECK-PWR9-NEXT: lxv v21, 48(r1) # 16-byte Folded Reload
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; CHECK-PWR9-NEXT: lxv v20, 32(r1) # 16-byte Folded Reload
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; CHECK-PWR9-NEXT: addi r1, r1, 224
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; CHECK-PWR9-NEXT: ld r0, 16(r1)
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; CHECK-PWR9-NEXT: mtlr r0
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; CHECK-PWR9-NEXT: blr
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entry:
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%0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{v20},~{v21}"(i32 %a, i32 %b)
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%call = tail call signext i32 @callee(i32 signext %0)
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ret i32 %call
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}
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define dso_local signext i32 @caller4(i32 signext %a, i32 signext %b) local_unnamed_addr {
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; CHECK-PWR8-LABEL: caller4:
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; CHECK-PWR8: # %bb.0: # %entry
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; CHECK-PWR8-NEXT: mflr r0
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; CHECK-PWR8-NEXT: std r0, 16(r1)
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; CHECK-PWR8-NEXT: stdu r1, -32(r1)
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; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 32
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; CHECK-PWR8-NEXT: .cfi_offset lr, 16
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; CHECK-PWR8-NEXT: #APP
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; CHECK-PWR8-NEXT: add r3, r3, r4
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; CHECK-PWR8-NEXT: #NO_APP
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; CHECK-PWR8-NEXT: extsw r3, r3
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; CHECK-PWR8-NEXT: bl callee
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; CHECK-PWR8-NEXT: nop
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; CHECK-PWR8-NEXT: addi r1, r1, 32
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; CHECK-PWR8-NEXT: ld r0, 16(r1)
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; CHECK-PWR8-NEXT: mtlr r0
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; CHECK-PWR8-NEXT: blr
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;
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; CHECK-PWR9-LABEL: caller4:
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; CHECK-PWR9: # %bb.0: # %entry
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; CHECK-PWR9-NEXT: mflr r0
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; CHECK-PWR9-NEXT: std r0, 16(r1)
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; CHECK-PWR9-NEXT: stdu r1, -32(r1)
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; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 32
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; CHECK-PWR9-NEXT: .cfi_offset lr, 16
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; CHECK-PWR9-NEXT: #APP
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; CHECK-PWR9-NEXT: add r3, r3, r4
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; CHECK-PWR9-NEXT: #NO_APP
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; CHECK-PWR9-NEXT: extsw r3, r3
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; CHECK-PWR9-NEXT: bl callee
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; CHECK-PWR9-NEXT: nop
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; CHECK-PWR9-NEXT: addi r1, r1, 32
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; CHECK-PWR9-NEXT: ld r0, 16(r1)
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; CHECK-PWR9-NEXT: mtlr r0
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; CHECK-PWR9-NEXT: blr
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entry:
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%0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{vs52},~{vs53}"(i32 %a, i32 %b)
214+
%call = tail call signext i32 @callee(i32 signext %0)
215+
ret i32 %call
216+
}
217+
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define dso_local signext i32 @caller_mixed(i32 signext %a, i32 signext %b) local_unnamed_addr {
219+
; CHECK-PWR8-LABEL: caller_mixed:
220+
; CHECK-PWR8: # %bb.0: # %entry
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; CHECK-PWR8-NEXT: mflr r0
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; CHECK-PWR8-NEXT: std r0, 16(r1)
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; CHECK-PWR8-NEXT: stdu r1, -528(r1)
224+
; CHECK-PWR8-NEXT: .cfi_def_cfa_offset 528
225+
; CHECK-PWR8-NEXT: .cfi_offset lr, 16
226+
; CHECK-PWR8-NEXT: .cfi_offset r14, -288
227+
; CHECK-PWR8-NEXT: .cfi_offset f14, -144
228+
; CHECK-PWR8-NEXT: .cfi_offset v20, -480
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; CHECK-PWR8-NEXT: li r5, 48
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; CHECK-PWR8-NEXT: std r14, 240(r1) # 8-byte Folded Spill
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; CHECK-PWR8-NEXT: stfd f14, 384(r1) # 8-byte Folded Spill
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; CHECK-PWR8-NEXT: stxvd2x v20, r1, r5 # 16-byte Folded Spill
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; CHECK-PWR8-NEXT: #APP
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; CHECK-PWR8-NEXT: add r3, r3, r4
235+
; CHECK-PWR8-NEXT: #NO_APP
236+
; CHECK-PWR8-NEXT: extsw r3, r3
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; CHECK-PWR8-NEXT: bl callee
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; CHECK-PWR8-NEXT: nop
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; CHECK-PWR8-NEXT: li r4, 48
240+
; CHECK-PWR8-NEXT: lfd f14, 384(r1) # 8-byte Folded Reload
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; CHECK-PWR8-NEXT: ld r14, 240(r1) # 8-byte Folded Reload
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; CHECK-PWR8-NEXT: lxvd2x v20, r1, r4 # 16-byte Folded Reload
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; CHECK-PWR8-NEXT: addi r1, r1, 528
244+
; CHECK-PWR8-NEXT: ld r0, 16(r1)
245+
; CHECK-PWR8-NEXT: mtlr r0
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; CHECK-PWR8-NEXT: blr
247+
;
248+
; CHECK-PWR9-LABEL: caller_mixed:
249+
; CHECK-PWR9: # %bb.0: # %entry
250+
; CHECK-PWR9-NEXT: mflr r0
251+
; CHECK-PWR9-NEXT: std r0, 16(r1)
252+
; CHECK-PWR9-NEXT: stdu r1, -512(r1)
253+
; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 512
254+
; CHECK-PWR9-NEXT: .cfi_offset lr, 16
255+
; CHECK-PWR9-NEXT: .cfi_offset r14, -288
256+
; CHECK-PWR9-NEXT: .cfi_offset f14, -144
257+
; CHECK-PWR9-NEXT: .cfi_offset v20, -480
258+
; CHECK-PWR9-NEXT: std r14, 224(r1) # 8-byte Folded Spill
259+
; CHECK-PWR9-NEXT: stfd f14, 368(r1) # 8-byte Folded Spill
260+
; CHECK-PWR9-NEXT: stxv v20, 32(r1) # 16-byte Folded Spill
261+
; CHECK-PWR9-NEXT: #APP
262+
; CHECK-PWR9-NEXT: add r3, r3, r4
263+
; CHECK-PWR9-NEXT: #NO_APP
264+
; CHECK-PWR9-NEXT: extsw r3, r3
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; CHECK-PWR9-NEXT: bl callee
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; CHECK-PWR9-NEXT: nop
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; CHECK-PWR9-NEXT: lxv v20, 32(r1) # 16-byte Folded Reload
268+
; CHECK-PWR9-NEXT: lfd f14, 368(r1) # 8-byte Folded Reload
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; CHECK-PWR9-NEXT: ld r14, 224(r1) # 8-byte Folded Reload
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; CHECK-PWR9-NEXT: addi r1, r1, 512
271+
; CHECK-PWR9-NEXT: ld r0, 16(r1)
272+
; CHECK-PWR9-NEXT: mtlr r0
273+
; CHECK-PWR9-NEXT: blr
274+
entry:
275+
%0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{f14},~{v20},~{vs53}"(i32 %a, i32 %b)
276+
%call = tail call signext i32 @callee(i32 signext %0)
277+
ret i32 %call
278+
}
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‎llvm/test/CodeGen/PowerPC/larger-than-red-zone.ll

Lines changed: 88 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,88 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
3+
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
4+
5+
define dso_local signext i32 @caller(i32 signext %a, i32 signext %b) local_unnamed_addr {
6+
; CHECK-LABEL: caller:
7+
; CHECK: # %bb.0: # %entry
8+
; CHECK-NEXT: mflr r0
9+
; CHECK-NEXT: std r0, 16(r1)
10+
; CHECK-NEXT: stdu r1, -320(r1)
11+
; CHECK-NEXT: .cfi_def_cfa_offset 320
12+
; CHECK-NEXT: .cfi_offset lr, 16
13+
; CHECK-NEXT: .cfi_offset r14, -288
14+
; CHECK-NEXT: .cfi_offset r15, -280
15+
; CHECK-NEXT: .cfi_offset r16, -272
16+
; CHECK-NEXT: .cfi_offset r17, -264
17+
; CHECK-NEXT: .cfi_offset r18, -256
18+
; CHECK-NEXT: .cfi_offset r19, -248
19+
; CHECK-NEXT: .cfi_offset r20, -240
20+
; CHECK-NEXT: .cfi_offset r21, -232
21+
; CHECK-NEXT: .cfi_offset r22, -224
22+
; CHECK-NEXT: .cfi_offset r23, -216
23+
; CHECK-NEXT: .cfi_offset r24, -208
24+
; CHECK-NEXT: .cfi_offset r25, -200
25+
; CHECK-NEXT: .cfi_offset r26, -192
26+
; CHECK-NEXT: .cfi_offset r27, -184
27+
; CHECK-NEXT: .cfi_offset r28, -176
28+
; CHECK-NEXT: .cfi_offset r29, -168
29+
; CHECK-NEXT: .cfi_offset r30, -160
30+
; CHECK-NEXT: .cfi_offset r31, -152
31+
; CHECK-NEXT: .cfi_offset f14, -144
32+
; CHECK-NEXT: std r14, 32(r1) # 8-byte Folded Spill
33+
; CHECK-NEXT: std r15, 40(r1) # 8-byte Folded Spill
34+
; CHECK-NEXT: std r16, 48(r1) # 8-byte Folded Spill
35+
; CHECK-NEXT: std r17, 56(r1) # 8-byte Folded Spill
36+
; CHECK-NEXT: std r18, 64(r1) # 8-byte Folded Spill
37+
; CHECK-NEXT: std r19, 72(r1) # 8-byte Folded Spill
38+
; CHECK-NEXT: std r20, 80(r1) # 8-byte Folded Spill
39+
; CHECK-NEXT: std r21, 88(r1) # 8-byte Folded Spill
40+
; CHECK-NEXT: std r22, 96(r1) # 8-byte Folded Spill
41+
; CHECK-NEXT: std r23, 104(r1) # 8-byte Folded Spill
42+
; CHECK-NEXT: std r24, 112(r1) # 8-byte Folded Spill
43+
; CHECK-NEXT: std r25, 120(r1) # 8-byte Folded Spill
44+
; CHECK-NEXT: std r26, 128(r1) # 8-byte Folded Spill
45+
; CHECK-NEXT: std r27, 136(r1) # 8-byte Folded Spill
46+
; CHECK-NEXT: std r28, 144(r1) # 8-byte Folded Spill
47+
; CHECK-NEXT: std r29, 152(r1) # 8-byte Folded Spill
48+
; CHECK-NEXT: std r30, 160(r1) # 8-byte Folded Spill
49+
; CHECK-NEXT: std r31, 168(r1) # 8-byte Folded Spill
50+
; CHECK-NEXT: stfd f14, 176(r1) # 8-byte Folded Spill
51+
; CHECK-NEXT: #APP
52+
; CHECK-NEXT: add r3, r3, r4
53+
; CHECK-NEXT: #NO_APP
54+
; CHECK-NEXT: extsw r3, r3
55+
; CHECK-NEXT: bl callee
56+
; CHECK-NEXT: nop
57+
; CHECK-NEXT: lfd f14, 176(r1) # 8-byte Folded Reload
58+
; CHECK-NEXT: ld r31, 168(r1) # 8-byte Folded Reload
59+
; CHECK-NEXT: ld r30, 160(r1) # 8-byte Folded Reload
60+
; CHECK-NEXT: ld r29, 152(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r28, 144(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r27, 136(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r26, 128(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r25, 120(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r24, 112(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r23, 104(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r22, 96(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r21, 88(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r20, 80(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r19, 72(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r18, 64(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r17, 56(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r16, 48(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r15, 40(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r14, 32(r1) # 8-byte Folded Reload
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; CHECK-NEXT: addi r1, r1, 320
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31},~{f14}"(i32 %a, i32 %b)
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%call = tail call signext i32 @callee(i32 signext %0)
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ret i32 %call
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}
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declare signext i32 @callee(i32 signext) local_unnamed_addr
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