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[RISCV] Add test for strided gather with recursive disjoint or. NFC
This already gets converted to a strided intrinsic because we currently call haveNoCommonBitsSet when checking or instructions, but an upcoming patch will change this logic and we want to preserve this case. Note that this IR is in the form that comes from instcombine. The splats need to be inline constexprs, otherwise isSplatValue() will fail. (It can't currently handle splats where the shufflevector is an instruction, and the insertelement is a constexpr.
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llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll

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@@ -49,6 +49,58 @@ for.cond.cleanup: ; preds = %vector.body
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ret <vscale x 1 x i64> %accum.next
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}
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define <vscale x 1 x i64> @gather_disjoint_or(ptr %a, i64 %len) {
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; CHECK-LABEL: @gather_disjoint_or(
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; CHECK-NEXT: vector.ph:
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; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_IND_SCALAR:%.*]] = phi i64 [ 1, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT_SCALAR:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[ACCUM:%.*]] = phi <vscale x 1 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[ACCUM_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i64, ptr [[A:%.*]], i64 [[VEC_IND_SCALAR]]
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; CHECK-NEXT: [[GATHER:%.*]] = call <vscale x 1 x i64> @llvm.riscv.masked.strided.load.nxv1i64.p0.i64(<vscale x 1 x i64> poison, ptr [[TMP0]], i64 16, <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i32 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer))
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; CHECK-NEXT: [[ACCUM_NEXT]] = add <vscale x 1 x i64> [[ACCUM]], [[GATHER]]
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[VSCALE]]
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; CHECK-NEXT: [[VEC_IND_NEXT_SCALAR]] = add i64 [[VEC_IND_SCALAR]], 2
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; CHECK-NEXT: [[EXIT:%.*]] = icmp ne i64 [[INDEX_NEXT]], [[LEN:%.*]]
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; CHECK-NEXT: br i1 [[EXIT]], label [[FOR_COND_CLEANUP:%.*]], label [[VECTOR_BODY]]
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; CHECK: for.cond.cleanup:
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; CHECK-NEXT: ret <vscale x 1 x i64> [[ACCUM_NEXT]]
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;
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vector.ph:
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%vscale = call i64 @llvm.vscale.i64()
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%step = tail call <vscale x 1 x i64> @llvm.experimental.stepvector.nxv1i64()
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%step.mul2 = shl <vscale x 1 x i64> %step, shufflevector(<vscale x 1 x i64> insertelement(<vscale x 1 x i64> poison, i64 1, i32 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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%vec.ind = phi <vscale x 1 x i64> [ %step.mul2, %vector.ph ], [ %vec.ind.next, %vector.body ]
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%accum = phi <vscale x 1 x i64> [ zeroinitializer, %vector.ph ], [ %accum.next, %vector.body ]
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%vec.ind.or = or disjoint <vscale x 1 x i64> %vec.ind, shufflevector(<vscale x 1 x i64> insertelement(<vscale x 1 x i64> poison, i64 1, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
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%gep = getelementptr i64, ptr %a, <vscale x 1 x i64> %vec.ind.or
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%gather = call <vscale x 1 x i64> @llvm.masked.gather.nxv1i64.nxv1p0(
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<vscale x 1 x ptr> %gep,
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i32 8,
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<vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i32 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer),
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<vscale x 1 x i64> poison
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)
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%accum.next = add <vscale x 1 x i64> %accum, %gather
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%index.next = add nuw i64 %index, %vscale
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%vec.ind.next = add <vscale x 1 x i64> %vec.ind, shufflevector(<vscale x 1 x i64> insertelement(<vscale x 1 x i64> poison, i64 2, i64 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)
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%exit = icmp ne i64 %index.next, %len
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br i1 %exit, label %for.cond.cleanup, label %vector.body
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for.cond.cleanup: ; preds = %vector.body
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ret <vscale x 1 x i64> %accum.next
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}
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define void @scatter(ptr %a, i32 %len) {
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; CHECK-LABEL: @scatter(
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; CHECK-NEXT: vector.ph:

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