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[LSR][NFC] Add pre-commit test
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -S -loop-reduce %s | FileCheck %s
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; REQUIRES: x86-registered-target
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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define i64 @test_duplicated_phis(i64 noundef %N) {
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; CHECK-LABEL: define i64 @test_duplicated_phis(
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; CHECK-SAME: i64 noundef [[N:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: [[MUL:%.*]] = shl i64 [[N]], 1
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; CHECK-NEXT: [[CMP6_NOT:%.*]] = icmp eq i64 [[MUL]], 0
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; CHECK-NEXT: br i1 [[CMP6_NOT]], label %[[FOR_END:.*]], label %[[FOR_BODY_PREHEADER:.*]]
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; CHECK: [[FOR_BODY_PREHEADER]]:
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; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i64 [[MUL]], 4
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; CHECK-NEXT: br i1 [[TMP0]], label %[[FOR_END_LOOPEXIT_UNR_LCSSA:.*]], label %[[FOR_BODY_PREHEADER_NEW:.*]]
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; CHECK: [[FOR_BODY_PREHEADER_NEW]]:
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; CHECK-NEXT: [[UNROLL_ITER:%.*]] = and i64 [[MUL]], -4
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; CHECK-NEXT: br label %[[FOR_BODY:.*]]
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; CHECK: [[FOR_BODY]]:
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; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], %[[FOR_BODY]] ], [ -1, %[[FOR_BODY_PREHEADER_NEW]] ]
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; CHECK-NEXT: [[I_07:%.*]] = phi i64 [ 0, %[[FOR_BODY_PREHEADER_NEW]] ], [ [[INC_3:%.*]], %[[FOR_BODY]] ]
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; CHECK-NEXT: [[INC_3]] = add i64 [[I_07]], 4
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; CHECK-NEXT: [[LSR_IV_NEXT]] = add i64 [[LSR_IV]], -2
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; CHECK-NEXT: [[NITER_NCMP_3_NOT:%.*]] = icmp eq i64 [[UNROLL_ITER]], [[INC_3]]
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; CHECK-NEXT: br i1 [[NITER_NCMP_3_NOT]], label %[[FOR_END_LOOPEXIT_UNR_LCSSA_LOOPEXIT:.*]], label %[[FOR_BODY]]
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; CHECK: [[FOR_END_LOOPEXIT_UNR_LCSSA_LOOPEXIT]]:
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; CHECK-NEXT: [[LSR_IV_NEXT_LCSSA:%.*]] = phi i64 [ [[LSR_IV_NEXT]], %[[FOR_BODY]] ]
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; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[LSR_IV_NEXT]], 1
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; CHECK-NEXT: br label %[[FOR_END_LOOPEXIT_UNR_LCSSA]]
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; CHECK: [[FOR_END_LOOPEXIT_UNR_LCSSA]]:
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; CHECK-NEXT: [[RES_1_LCSSA_PH:%.*]] = phi i64 [ undef, %[[FOR_BODY_PREHEADER]] ], [ [[TMP1]], %[[FOR_END_LOOPEXIT_UNR_LCSSA_LOOPEXIT]] ]
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; CHECK-NEXT: [[RES_09_UNR:%.*]] = phi i64 [ -1, %[[FOR_BODY_PREHEADER]] ], [ [[LSR_IV_NEXT_LCSSA]], %[[FOR_END_LOOPEXIT_UNR_LCSSA_LOOPEXIT]] ]
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; CHECK-NEXT: [[TMP2:%.*]] = and i64 [[N]], 1
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; CHECK-NEXT: [[LCMP_MOD_NOT:%.*]] = icmp eq i64 [[TMP2]], 0
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; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[LCMP_MOD_NOT]], i64 [[RES_1_LCSSA_PH]], i64 [[RES_09_UNR]]
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; CHECK-NEXT: br label %[[FOR_END]]
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; CHECK: [[FOR_END]]:
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; CHECK-NEXT: [[RES_0_LCSSA:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[SPEC_SELECT]], %[[FOR_END_LOOPEXIT_UNR_LCSSA]] ]
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; CHECK-NEXT: ret i64 [[RES_0_LCSSA]]
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;
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entry:
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%mul = shl i64 %N, 1
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%cmp6.not = icmp eq i64 %mul, 0
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br i1 %cmp6.not, label %for.end, label %for.body.preheader
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for.body.preheader:
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%0 = icmp ult i64 %mul, 4
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br i1 %0, label %for.end.loopexit.unr-lcssa, label %for.body.preheader.new
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for.body.preheader.new:
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%unroll_iter = and i64 %mul, -4
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br label %for.body
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for.body:
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%res.09 = phi i64 [ 0, %for.body.preheader.new ], [ %res.1.3, %for.body ]
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%i.07 = phi i64 [ 0, %for.body.preheader.new ], [ %inc.3, %for.body ]
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%niter = phi i64 [ 0, %for.body.preheader.new ], [ %niter.next.3, %for.body ]
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%res.1.1 = add i64 %res.09, -1
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%inc.1 = or disjoint i64 %i.07, 2
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%res.1.2 = add i64 %inc.1, %res.1.1
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%reass.sub = sub i64 %res.1.2, %i.07
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%res.1.3 = add i64 %reass.sub, -3
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%inc.3 = add nuw i64 %i.07, 4
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%niter.next.3 = add i64 %niter, 4
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%niter.ncmp.3.not = icmp eq i64 %niter.next.3, %unroll_iter
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br i1 %niter.ncmp.3.not, label %for.end.loopexit.unr-lcssa.loopexit, label %for.body
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for.end.loopexit.unr-lcssa.loopexit:
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%1 = add i64 %reass.sub, -4
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br label %for.end.loopexit.unr-lcssa
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for.end.loopexit.unr-lcssa:
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%res.1.lcssa.ph = phi i64 [ undef, %for.body.preheader ], [ %res.1.3, %for.end.loopexit.unr-lcssa.loopexit ]
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%res.09.unr = phi i64 [ -1, %for.body.preheader ], [ %1, %for.end.loopexit.unr-lcssa.loopexit ]
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%2 = and i64 %N, 1
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%lcmp.mod.not = icmp eq i64 %2, 0
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%spec.select = select i1 %lcmp.mod.not, i64 %res.1.lcssa.ph, i64 %res.09.unr
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br label %for.end
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for.end:
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%res.0.lcssa = phi i64 [ 0, %entry ], [ %spec.select, %for.end.loopexit.unr-lcssa ]
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ret i64 %res.0.lcssa
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}

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