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[RISCV][NFC] Add base classes of Operand and uimm/simm (#68472)
To simplify code.
1 parent 11caef0 commit 18622fc

8 files changed

+70
-147
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 42 additions & 79 deletions
Original file line numberDiff line numberDiff line change
@@ -149,18 +149,40 @@ class UImmAsmOperand<int width, string suffix = "">
149149
: ImmAsmOperand<"U", width, suffix> {
150150
}
151151

152+
class RISCVOp<ValueType vt = XLenVT> : Operand<vt> {
153+
let OperandNamespace = "RISCVOp";
154+
}
155+
156+
class RISCVUImmOp<int bitsNum> : RISCVOp {
157+
let ParserMatchClass = UImmAsmOperand<bitsNum>;
158+
let DecoderMethod = "decodeUImmOperand<" # bitsNum # ">";
159+
let OperandType = "OPERAND_UIMM" # bitsNum;
160+
}
161+
162+
class RISCVUImmLeafOp<int bitsNum> :
163+
RISCVUImmOp<bitsNum>, ImmLeaf<XLenVT, "return isUInt<" # bitsNum # ">(Imm);">;
164+
165+
class RISCVSImmOp<int bitsNum> : RISCVOp {
166+
let ParserMatchClass = SImmAsmOperand<bitsNum>;
167+
let EncoderMethod = "getImmOpValue";
168+
let DecoderMethod = "decodeSImmOperand<" # bitsNum # ">";
169+
let OperandType = "OPERAND_SIMM" # bitsNum;
170+
}
171+
172+
class RISCVSImmLeafOp<int bitsNum > :
173+
RISCVSImmOp<bitsNum>, ImmLeaf<XLenVT, "return isInt<" # bitsNum # ">(Imm);">;
174+
152175
def FenceArg : AsmOperandClass {
153176
let Name = "FenceArg";
154177
let RenderMethod = "addFenceArgOperands";
155178
let ParserMethod = "parseFenceArg";
156179
}
157180

158-
def fencearg : Operand<XLenVT> {
181+
def fencearg : RISCVOp {
159182
let ParserMatchClass = FenceArg;
160183
let PrintMethod = "printFenceArg";
161184
let DecoderMethod = "decodeUImmOperand<4>";
162185
let OperandType = "OPERAND_UIMM4";
163-
let OperandNamespace = "RISCVOp";
164186
}
165187

166188
def UImmLog2XLenAsmOperand : AsmOperandClass {
@@ -169,7 +191,7 @@ def UImmLog2XLenAsmOperand : AsmOperandClass {
169191
let DiagnosticType = "InvalidUImmLog2XLen";
170192
}
171193

172-
def uimmlog2xlen : Operand<XLenVT>, ImmLeaf<XLenVT, [{
194+
def uimmlog2xlen : RISCVOp, ImmLeaf<XLenVT, [{
173195
if (Subtarget->is64Bit())
174196
return isUInt<6>(Imm);
175197
return isUInt<5>(Imm);
@@ -186,97 +208,40 @@ def uimmlog2xlen : Operand<XLenVT>, ImmLeaf<XLenVT, [{
186208
return isUInt<5>(Imm);
187209
}];
188210
let OperandType = "OPERAND_UIMMLOG2XLEN";
189-
let OperandNamespace = "RISCVOp";
190211
}
191212

192-
def uimm1 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<1>(Imm);}]> {
193-
let ParserMatchClass = UImmAsmOperand<1>;
194-
let DecoderMethod = "decodeUImmOperand<1>";
195-
let OperandType = "OPERAND_UIMM1";
196-
let OperandNamespace = "RISCVOp";
213+
def InsnDirectiveOpcode : AsmOperandClass {
214+
let Name = "InsnDirectiveOpcode";
215+
let ParserMethod = "parseInsnDirectiveOpcode";
216+
let RenderMethod = "addImmOperands";
217+
let PredicateMethod = "isImm";
197218
}
198219

199-
def uimm2 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<2>(Imm);}]> {
200-
let ParserMatchClass = UImmAsmOperand<2>;
201-
let DecoderMethod = "decodeUImmOperand<2>";
202-
let OperandType = "OPERAND_UIMM2";
203-
let OperandNamespace = "RISCVOp";
220+
def uimm1 : RISCVUImmLeafOp<1>;
221+
def uimm2 : RISCVUImmLeafOp<2> {
204222
let MCOperandPredicate = [{
205223
int64_t Imm;
206224
if (!MCOp.evaluateAsConstantImm(Imm))
207225
return false;
208226
return isUInt<2>(Imm);
209227
}];
210228
}
211-
212-
def uimm3 : Operand<XLenVT> {
213-
let ParserMatchClass = UImmAsmOperand<3>;
214-
let DecoderMethod = "decodeUImmOperand<3>";
215-
let OperandType = "OPERAND_UIMM3";
216-
let OperandNamespace = "RISCVOp";
217-
}
218-
219-
def uimm4 : Operand<XLenVT> {
220-
let ParserMatchClass = UImmAsmOperand<4>;
221-
let DecoderMethod = "decodeUImmOperand<4>";
222-
let OperandType = "OPERAND_UIMM4";
223-
let OperandNamespace = "RISCVOp";
224-
}
225-
226-
def uimm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]> {
227-
let ParserMatchClass = UImmAsmOperand<5>;
228-
let DecoderMethod = "decodeUImmOperand<5>";
229-
let OperandType = "OPERAND_UIMM5";
230-
let OperandNamespace = "RISCVOp";
231-
}
232-
233-
def InsnDirectiveOpcode : AsmOperandClass {
234-
let Name = "InsnDirectiveOpcode";
235-
let ParserMethod = "parseInsnDirectiveOpcode";
236-
let RenderMethod = "addImmOperands";
237-
let PredicateMethod = "isImm";
238-
}
239-
240-
def uimm6 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<6>(Imm);}]> {
241-
let ParserMatchClass = UImmAsmOperand<6>;
242-
let DecoderMethod = "decodeUImmOperand<6>";
243-
let OperandType = "OPERAND_UIMM6";
244-
let OperandNamespace = "RISCVOp";
245-
}
246-
247-
def uimm7_opcode : Operand<XLenVT> {
229+
def uimm3 : RISCVUImmOp<3>;
230+
def uimm4 : RISCVUImmOp<4>;
231+
def uimm5 : RISCVUImmLeafOp<5>;
232+
def uimm6 : RISCVUImmLeafOp<6>;
233+
def uimm7_opcode : RISCVUImmOp<7> {
248234
let ParserMatchClass = InsnDirectiveOpcode;
249-
let DecoderMethod = "decodeUImmOperand<7>";
250-
let OperandType = "OPERAND_UIMM7";
251-
let OperandNamespace = "RISCVOp";
252235
}
253-
254-
def uimm7 : Operand<XLenVT> {
255-
let ParserMatchClass = UImmAsmOperand<7>;
256-
let DecoderMethod = "decodeUImmOperand<7>";
257-
let OperandType = "OPERAND_UIMM7";
258-
let OperandNamespace = "RISCVOp";
259-
}
260-
261-
def uimm8 : Operand<XLenVT> {
262-
let ParserMatchClass = UImmAsmOperand<8>;
263-
let DecoderMethod = "decodeUImmOperand<8>";
264-
let OperandType = "OPERAND_UIMM8";
265-
let OperandNamespace = "RISCVOp";
266-
}
267-
268-
def simm12 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<12>(Imm);}]> {
269-
let ParserMatchClass = SImmAsmOperand<12>;
270-
let EncoderMethod = "getImmOpValue";
271-
let DecoderMethod = "decodeSImmOperand<12>";
236+
def uimm7 : RISCVUImmOp<7>;
237+
def uimm8 : RISCVUImmOp<8>;
238+
def simm12 : RISCVSImmLeafOp<12> {
272239
let MCOperandPredicate = [{
273240
int64_t Imm;
274241
if (MCOp.evaluateAsConstantImm(Imm))
275242
return isInt<12>(Imm);
276243
return MCOp.isBareSymbolRef();
277244
}];
278-
let OperandType = "OPERAND_SIMM12";
279-
let OperandNamespace = "RISCVOp";
280245
}
281246

282247
// A 12-bit signed immediate which cannot fit in 6-bit signed immediate,
@@ -299,11 +264,10 @@ def simm13_lsb0 : Operand<OtherVT> {
299264
let OperandType = "OPERAND_PCREL";
300265
}
301266

302-
class UImm20Operand : Operand<XLenVT> {
267+
class UImm20Operand : RISCVOp {
303268
let EncoderMethod = "getImmOpValue";
304269
let DecoderMethod = "decodeUImmOperand<20>";
305270
let OperandType = "OPERAND_UIMM20";
306-
let OperandNamespace = "RISCVOp";
307271
}
308272

309273
class UImm20OperandMaybeSym : UImm20Operand {
@@ -405,12 +369,11 @@ def CSRSystemRegister : AsmOperandClass {
405369
let DiagnosticType = "InvalidCSRSystemRegister";
406370
}
407371

408-
def csr_sysreg : Operand<XLenVT> {
372+
def csr_sysreg : RISCVOp {
409373
let ParserMatchClass = CSRSystemRegister;
410374
let PrintMethod = "printCSRSystemRegister";
411375
let DecoderMethod = "decodeUImmOperand<12>";
412376
let OperandType = "OPERAND_UIMM12";
413-
let OperandNamespace = "RISCVOp";
414377
}
415378

416379
// A parameterized register class alternative to i32imm/i64imm from Target.td.

‎llvm/lib/Target/RISCV/RISCVInstrInfoC.td

Lines changed: 12 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ def UImmLog2XLenNonZeroAsmOperand : AsmOperandClass {
1818
let DiagnosticType = "InvalidUImmLog2XLenNonZero";
1919
}
2020

21-
def uimmlog2xlennonzero : Operand<XLenVT>, ImmLeaf<XLenVT, [{
21+
def uimmlog2xlennonzero : RISCVOp, ImmLeaf<XLenVT, [{
2222
if (Subtarget->is64Bit())
2323
return isUInt<6>(Imm) && (Imm != 0);
2424
return isUInt<5>(Imm) && (Imm != 0);
@@ -27,7 +27,6 @@ def uimmlog2xlennonzero : Operand<XLenVT>, ImmLeaf<XLenVT, [{
2727
// TODO: should ensure invalid shamt is rejected when decoding.
2828
let DecoderMethod = "decodeUImmNonZeroOperand<6>";
2929
let OperandType = "OPERAND_UIMMLOG2XLEN_NONZERO";
30-
let OperandNamespace = "RISCVOp";
3130
let MCOperandPredicate = [{
3231
int64_t Imm;
3332
if (!MCOp.evaluateAsConstantImm(Imm))
@@ -38,12 +37,7 @@ def uimmlog2xlennonzero : Operand<XLenVT>, ImmLeaf<XLenVT, [{
3837
}];
3938
}
4039

41-
def simm6 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<6>(Imm);}]> {
42-
let ParserMatchClass = SImmAsmOperand<6>;
43-
let EncoderMethod = "getImmOpValue";
44-
let DecoderMethod = "decodeSImmOperand<6>";
45-
let OperandType = "OPERAND_SIMM6";
46-
let OperandNamespace = "RISCVOp";
40+
def simm6 : RISCVSImmLeafOp<6> {
4741
let MCOperandPredicate = [{
4842
int64_t Imm;
4943
if (MCOp.evaluateAsConstantImm(Imm))
@@ -52,13 +46,12 @@ def simm6 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<6>(Imm);}]> {
5246
}];
5347
}
5448

55-
def simm6nonzero : Operand<XLenVT>,
49+
def simm6nonzero : RISCVOp,
5650
ImmLeaf<XLenVT, [{return (Imm != 0) && isInt<6>(Imm);}]> {
5751
let ParserMatchClass = SImmAsmOperand<6, "NonZero">;
5852
let EncoderMethod = "getImmOpValue";
5953
let DecoderMethod = "decodeSImmNonZeroOperand<6>";
6054
let OperandType = "OPERAND_SIMM6_NONZERO";
61-
let OperandNamespace = "RISCVOp";
6255
let MCOperandPredicate = [{
6356
int64_t Imm;
6457
if (MCOp.evaluateAsConstantImm(Imm))
@@ -67,11 +60,10 @@ def simm6nonzero : Operand<XLenVT>,
6760
}];
6861
}
6962

70-
def immzero : Operand<XLenVT>,
63+
def immzero : RISCVOp,
7164
ImmLeaf<XLenVT, [{return (Imm == 0);}]> {
7265
let ParserMatchClass = ImmZeroAsmOperand;
7366
let OperandType = "OPERAND_ZERO";
74-
let OperandNamespace = "RISCVOp";
7567
}
7668

7769
def CLUIImmAsmOperand : AsmOperandClass {
@@ -86,15 +78,14 @@ def CLUIImmAsmOperand : AsmOperandClass {
8678
// loaded in to bits 17-12 of the destination register and sign extended from
8779
// bit 17. Therefore, this 6-bit immediate can represent values in the ranges
8880
// [1, 31] and [0xfffe0, 0xfffff].
89-
def c_lui_imm : Operand<XLenVT>,
81+
def c_lui_imm : RISCVOp,
9082
ImmLeaf<XLenVT, [{return (Imm != 0) &&
9183
(isUInt<5>(Imm) ||
9284
(Imm >= 0xfffe0 && Imm <= 0xfffff));}]> {
9385
let ParserMatchClass = CLUIImmAsmOperand;
9486
let EncoderMethod = "getImmOpValue";
9587
let DecoderMethod = "decodeCLUIImmOperand";
9688
let OperandType = "OPERAND_CLUI_IMM";
97-
let OperandNamespace = "RISCVOp";
9889
let MCOperandPredicate = [{
9990
int64_t Imm;
10091
if (MCOp.evaluateAsConstantImm(Imm))
@@ -105,13 +96,12 @@ def c_lui_imm : Operand<XLenVT>,
10596
}
10697

10798
// A 7-bit unsigned immediate where the least significant two bits are zero.
108-
def uimm7_lsb00 : Operand<XLenVT>,
99+
def uimm7_lsb00 : RISCVOp,
109100
ImmLeaf<XLenVT, [{return isShiftedUInt<5, 2>(Imm);}]> {
110101
let ParserMatchClass = UImmAsmOperand<7, "Lsb00">;
111102
let EncoderMethod = "getImmOpValue";
112103
let DecoderMethod = "decodeUImmOperand<7>";
113104
let OperandType = "OPERAND_UIMM7_LSB00";
114-
let OperandNamespace = "RISCVOp";
115105
let MCOperandPredicate = [{
116106
int64_t Imm;
117107
if (!MCOp.evaluateAsConstantImm(Imm))
@@ -121,13 +111,12 @@ def uimm7_lsb00 : Operand<XLenVT>,
121111
}
122112

123113
// A 8-bit unsigned immediate where the least significant two bits are zero.
124-
def uimm8_lsb00 : Operand<XLenVT>,
114+
def uimm8_lsb00 : RISCVOp,
125115
ImmLeaf<XLenVT, [{return isShiftedUInt<6, 2>(Imm);}]> {
126116
let ParserMatchClass = UImmAsmOperand<8, "Lsb00">;
127117
let EncoderMethod = "getImmOpValue";
128118
let DecoderMethod = "decodeUImmOperand<8>";
129119
let OperandType = "OPERAND_UIMM8_LSB00";
130-
let OperandNamespace = "RISCVOp";
131120
let MCOperandPredicate = [{
132121
int64_t Imm;
133122
if (!MCOp.evaluateAsConstantImm(Imm))
@@ -137,13 +126,12 @@ def uimm8_lsb00 : Operand<XLenVT>,
137126
}
138127

139128
// A 8-bit unsigned immediate where the least significant three bits are zero.
140-
def uimm8_lsb000 : Operand<XLenVT>,
129+
def uimm8_lsb000 : RISCVOp,
141130
ImmLeaf<XLenVT, [{return isShiftedUInt<5, 3>(Imm);}]> {
142131
let ParserMatchClass = UImmAsmOperand<8, "Lsb000">;
143132
let EncoderMethod = "getImmOpValue";
144133
let DecoderMethod = "decodeUImmOperand<8>";
145134
let OperandType = "OPERAND_UIMM8_LSB000";
146-
let OperandNamespace = "RISCVOp";
147135
let MCOperandPredicate = [{
148136
int64_t Imm;
149137
if (!MCOp.evaluateAsConstantImm(Imm))
@@ -170,13 +158,12 @@ def simm9_lsb0 : Operand<OtherVT>,
170158
}
171159

172160
// A 9-bit unsigned immediate where the least significant three bits are zero.
173-
def uimm9_lsb000 : Operand<XLenVT>,
161+
def uimm9_lsb000 : RISCVOp,
174162
ImmLeaf<XLenVT, [{return isShiftedUInt<6, 3>(Imm);}]> {
175163
let ParserMatchClass = UImmAsmOperand<9, "Lsb000">;
176164
let EncoderMethod = "getImmOpValue";
177165
let DecoderMethod = "decodeUImmOperand<9>";
178166
let OperandType = "OPERAND_UIMM9_LSB000";
179-
let OperandNamespace = "RISCVOp";
180167
let MCOperandPredicate = [{
181168
int64_t Imm;
182169
if (!MCOp.evaluateAsConstantImm(Imm))
@@ -187,14 +174,13 @@ def uimm9_lsb000 : Operand<XLenVT>,
187174

188175
// A 10-bit unsigned immediate where the least significant two bits are zero
189176
// and the immediate can't be zero.
190-
def uimm10_lsb00nonzero : Operand<XLenVT>,
177+
def uimm10_lsb00nonzero : RISCVOp,
191178
ImmLeaf<XLenVT,
192179
[{return isShiftedUInt<8, 2>(Imm) && (Imm != 0);}]> {
193180
let ParserMatchClass = UImmAsmOperand<10, "Lsb00NonZero">;
194181
let EncoderMethod = "getImmOpValue";
195182
let DecoderMethod = "decodeUImmNonZeroOperand<10>";
196183
let OperandType = "OPERAND_UIMM10_LSB00_NONZERO";
197-
let OperandNamespace = "RISCVOp";
198184
let MCOperandPredicate = [{
199185
int64_t Imm;
200186
if (!MCOp.evaluateAsConstantImm(Imm))
@@ -204,14 +190,13 @@ def uimm10_lsb00nonzero : Operand<XLenVT>,
204190
}
205191

206192
// A 10-bit signed immediate where the least significant four bits are zero.
207-
def simm10_lsb0000nonzero : Operand<XLenVT>,
193+
def simm10_lsb0000nonzero : RISCVOp,
208194
ImmLeaf<XLenVT,
209195
[{return (Imm != 0) && isShiftedInt<6, 4>(Imm);}]> {
210196
let ParserMatchClass = SImmAsmOperand<10, "Lsb0000NonZero">;
211197
let EncoderMethod = "getImmOpValue";
212198
let DecoderMethod = "decodeSImmNonZeroOperand<10>";
213199
let OperandType = "OPERAND_SIMM10_LSB0000_NONZERO";
214-
let OperandNamespace = "RISCVOp";
215200
let MCOperandPredicate = [{
216201
int64_t Imm;
217202
if (!MCOp.evaluateAsConstantImm(Imm))
@@ -243,11 +228,10 @@ def InsnCDirectiveOpcode : AsmOperandClass {
243228
let PredicateMethod = "isImm";
244229
}
245230

246-
def uimm2_opcode : Operand<XLenVT> {
231+
def uimm2_opcode : RISCVOp {
247232
let ParserMatchClass = InsnCDirectiveOpcode;
248233
let DecoderMethod = "decodeUImmOperand<2>";
249234
let OperandType = "OPERAND_UIMM2";
250-
let OperandNamespace = "RISCVOp";
251235
}
252236

253237
//===----------------------------------------------------------------------===//

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