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[RISCV][GISel] Add missing fclass tests. NFC (#96694)
We were only testing f32 on rv32 and f64 on rv64. We need to test f32 and f64 on both rv32 and rv64.
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+258
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‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/is-fpclass-rv32.mir

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -80,3 +80,81 @@ body: |
8080
$x10 = COPY %7(s32)
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PseudoRET implicit $x10
8282
...
83+
---
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name: is_fpclass_f64
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $f10_d
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; CHECK-LABEL: name: is_fpclass_f64
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; CHECK: liveins: $f10_d
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
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; CHECK-NEXT: [[FCLASS_D:%[0-9]+]]:gpr = FCLASS_D [[COPY]]
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; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_D]], 152
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; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]]
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; CHECK-NEXT: $x10 = COPY [[SLTU]]
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:fprb(s64) = COPY $f10_d
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%3:gprb(s32) = G_CONSTANT i32 152
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%4:gprb(s32) = G_CONSTANT i32 0
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%5:gprb(s32) = G_FCLASS %0(s64)
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%6:gprb(s32) = G_AND %5, %3
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%7:gprb(s32) = G_ICMP intpred(ne), %6(s32), %4
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$x10 = COPY %7(s32)
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PseudoRET implicit $x10
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...
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---
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name: is_fpclass_f64_onehot
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $f10_d
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; CHECK-LABEL: name: is_fpclass_f64_onehot
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; CHECK: liveins: $f10_d
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
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; CHECK-NEXT: [[FCLASS_D:%[0-9]+]]:gpr = FCLASS_D [[COPY]]
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; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_D]], 256
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; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]]
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; CHECK-NEXT: $x10 = COPY [[SLTU]]
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:fprb(s64) = COPY $f10_d
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%3:gprb(s32) = G_CONSTANT i32 256
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%4:gprb(s32) = G_CONSTANT i32 0
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%5:gprb(s32) = G_FCLASS %0(s64)
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%6:gprb(s32) = G_AND %5, %3
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%7:gprb(s32) = G_ICMP intpred(ne), %6(s32), %4
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$x10 = COPY %7(s32)
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PseudoRET implicit $x10
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...
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---
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name: is_fpclass_f64_one
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $f10_d
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; CHECK-LABEL: name: is_fpclass_f64_one
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; CHECK: liveins: $f10_d
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
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; CHECK-NEXT: [[FCLASS_D:%[0-9]+]]:gpr = FCLASS_D [[COPY]]
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; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_D]], 1
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; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]]
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; CHECK-NEXT: $x10 = COPY [[SLTU]]
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:fprb(s64) = COPY $f10_d
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%3:gprb(s32) = G_CONSTANT i32 1
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%4:gprb(s32) = G_CONSTANT i32 0
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%5:gprb(s32) = G_FCLASS %0(s64)
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%6:gprb(s32) = G_AND %5, %3
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%7:gprb(s32) = G_ICMP intpred(ne), %6(s32), %4
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$x10 = COPY %7(s32)
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PseudoRET implicit $x10
160+
...

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/is-fpclass-rv64.mir

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,84 @@
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# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select -verify-machineinstrs %s -o - | \
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# RUN: FileCheck %s
44

5+
---
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name: is_fpclass_f32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $f10_f
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; CHECK-LABEL: name: is_fpclass_f32
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; CHECK: liveins: $f10_f
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
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; CHECK-NEXT: [[FCLASS_S:%[0-9]+]]:gpr = FCLASS_S [[COPY]]
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; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_S]], 152
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; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]]
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; CHECK-NEXT: $x10 = COPY [[SLTU]]
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:fprb(s32) = COPY $f10_f
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%3:gprb(s64) = G_CONSTANT i64 152
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%4:gprb(s64) = G_CONSTANT i64 0
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%5:gprb(s64) = G_FCLASS %0(s32)
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%6:gprb(s64) = G_AND %5, %3
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%7:gprb(s64) = G_ICMP intpred(ne), %6(s64), %4
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$x10 = COPY %7(s64)
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PseudoRET implicit $x10
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...
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---
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name: is_fpclass_f32_onehot
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $f10_f
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; CHECK-LABEL: name: is_fpclass_f32_onehot
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; CHECK: liveins: $f10_f
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
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; CHECK-NEXT: [[FCLASS_S:%[0-9]+]]:gpr = FCLASS_S [[COPY]]
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; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_S]], 256
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; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]]
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; CHECK-NEXT: $x10 = COPY [[SLTU]]
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:fprb(s32) = COPY $f10_f
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%3:gprb(s64) = G_CONSTANT i64 256
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%4:gprb(s64) = G_CONSTANT i64 0
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%5:gprb(s64) = G_FCLASS %0(s32)
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%6:gprb(s64) = G_AND %5, %3
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%7:gprb(s64) = G_ICMP intpred(ne), %6(s64), %4
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$x10 = COPY %7(s64)
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PseudoRET implicit $x10
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...
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---
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name: is_fpclass_f32_one
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $f10_f
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; CHECK-LABEL: name: is_fpclass_f32_one
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; CHECK: liveins: $f10_f
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
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; CHECK-NEXT: [[FCLASS_S:%[0-9]+]]:gpr = FCLASS_S [[COPY]]
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; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_S]], 1
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; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]]
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; CHECK-NEXT: $x10 = COPY [[SLTU]]
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:fprb(s32) = COPY $f10_f
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%3:gprb(s64) = G_CONSTANT i64 1
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%4:gprb(s64) = G_CONSTANT i64 0
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%5:gprb(s64) = G_FCLASS %0(s32)
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%6:gprb(s64) = G_AND %5, %3
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%7:gprb(s64) = G_ICMP intpred(ne), %6(s64), %4
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$x10 = COPY %7(s64)
81+
PseudoRET implicit $x10
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...
583
---
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name: is_fpclass_f64
785
legalized: true

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-is-fpclass-rv32.mir

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,3 +26,27 @@ body: |
2626
PseudoRET implicit $x10
2727
2828
...
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---
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name: is_fpclass_f64
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body: |
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bb.1:
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liveins: $f10_d
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; CHECK-LABEL: name: is_fpclass_f64
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; CHECK: liveins: $f10_d
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 152
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: [[FCLASS:%[0-9]+]]:_(s32) = G_FCLASS [[COPY]](s64)
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCLASS]], [[C]]
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[AND]](s32), [[C1]]
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; CHECK-NEXT: $x10 = COPY [[ICMP]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:_(s64) = COPY $f10_d
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%1:_(s1) = G_IS_FPCLASS %0(s64), 608
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%2:_(s32) = G_ANYEXT %1(s1)
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$x10 = COPY %2(s32)
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PseudoRET implicit $x10
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...

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-is-fpclass-rv64.mir

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,30 @@
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# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=legalizer %s -o - \
33
# RUN: | FileCheck %s
44

5+
---
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name: is_fpclass_f32
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body: |
8+
bb.1:
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liveins: $f10_f
10+
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; CHECK-LABEL: name: is_fpclass_f32
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; CHECK: liveins: $f10_f
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $f10_f
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 152
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; CHECK-NEXT: [[FCLASS:%[0-9]+]]:_(s64) = G_FCLASS [[COPY]](s32)
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[FCLASS]], [[C]]
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[AND]](s64), [[C1]]
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; CHECK-NEXT: $x10 = COPY [[ICMP]](s64)
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; CHECK-NEXT: PseudoRET implicit $x10
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%0:_(s32) = COPY $f10_f
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%1:_(s1) = G_IS_FPCLASS %0(s32), 608
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%2:_(s64) = G_ANYEXT %1(s1)
25+
$x10 = COPY %2(s64)
26+
PseudoRET implicit $x10
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28+
...
529
---
630
name: is_fpclass_f64
731
body: |

‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv32.mir

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,3 +29,30 @@ body: |
2929
$x10 = COPY %7(s32)
3030
PseudoRET implicit $x10
3131
...
32+
---
33+
name: is_fpclass_f64
34+
legalized: true
35+
body: |
36+
bb.0:
37+
liveins: $f10_d
38+
39+
; CHECK-LABEL: name: is_fpclass_f64
40+
; CHECK: liveins: $f10_d
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d
43+
; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 152
44+
; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: [[FCLASS:%[0-9]+]]:gprb(s32) = G_FCLASS [[COPY]](s64)
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; CHECK-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[FCLASS]], [[C]]
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ne), [[AND]](s32), [[C1]]
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; CHECK-NEXT: $x10 = COPY [[ICMP]](s32)
49+
; CHECK-NEXT: PseudoRET implicit $x10
50+
%0:_(s64) = COPY $f10_d
51+
%3:_(s32) = G_CONSTANT i32 152
52+
%4:_(s32) = G_CONSTANT i32 0
53+
%5:_(s32) = G_FCLASS %0(s64)
54+
%6:_(s32) = G_AND %5, %3
55+
%7:_(s32) = G_ICMP intpred(ne), %6(s32), %4
56+
$x10 = COPY %7(s32)
57+
PseudoRET implicit $x10
58+
...

‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-rv64.mir

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,33 @@
22
# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect -verify-machineinstrs %s -o - \
33
# RUN: | FileCheck %s
44

5+
---
6+
name: is_fpclass_f32
7+
legalized: true
8+
body: |
9+
bb.0:
10+
liveins: $f10_f
11+
12+
; CHECK-LABEL: name: is_fpclass_f32
13+
; CHECK: liveins: $f10_f
14+
; CHECK-NEXT: {{ $}}
15+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
16+
; CHECK-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 152
17+
; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 0
18+
; CHECK-NEXT: [[FCLASS:%[0-9]+]]:gprb(s64) = G_FCLASS [[COPY]](s32)
19+
; CHECK-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[FCLASS]], [[C]]
20+
; CHECK-NEXT: [[ICMP:%[0-9]+]]:gprb(s64) = G_ICMP intpred(ne), [[AND]](s64), [[C1]]
21+
; CHECK-NEXT: $x10 = COPY [[ICMP]](s64)
22+
; CHECK-NEXT: PseudoRET implicit $x10
23+
%0:_(s32) = COPY $f10_f
24+
%3:_(s64) = G_CONSTANT i64 152
25+
%4:_(s64) = G_CONSTANT i64 0
26+
%5:_(s64) = G_FCLASS %0(s32)
27+
%6:_(s64) = G_AND %5, %3
28+
%7:_(s64) = G_ICMP intpred(ne), %6(s64), %4
29+
$x10 = COPY %7(s64)
30+
PseudoRET implicit $x10
31+
...
532
---
633
name: is_fpclass_f64
734
legalized: true

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