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[RFC][SelectionDAG] Add and use SDNode::getAsZExtVal() helper (#76710)
This follows on from #76708, allowing `cast<ConstantSDNode>(N)->getZExtValue()` to be replaced with just `N->getAsZextVal();` Introduced via `git grep -l "cast<ConstantSDNode>\(.*\).*getZExtValue" | xargs sed -E -i 's/cast<ConstantSDNode>\((.*)\)->getZExtValue/\1->getAsZExtVal/'` and then using `git clang-format` on the result.
1 parent 4cb2ef4 commit 197214e

40 files changed

+159
-186
lines changed

‎llvm/include/llvm/CodeGen/SelectionDAGNodes.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -929,6 +929,9 @@ END_TWO_BYTE_PACK()
929929
/// Helper method returns the integer value of a ConstantSDNode operand.
930930
inline uint64_t getConstantOperandVal(unsigned Num) const;
931931

932+
/// Helper method returns the zero-extended integer value of a ConstantSDNode.
933+
inline uint64_t getAsZExtVal() const;
934+
932935
/// Helper method returns the APInt of a ConstantSDNode operand.
933936
inline const APInt &getConstantOperandAPInt(unsigned Num) const;
934937

@@ -1645,6 +1648,10 @@ uint64_t SDNode::getConstantOperandVal(unsigned Num) const {
16451648
return cast<ConstantSDNode>(getOperand(Num))->getZExtValue();
16461649
}
16471650

1651+
uint64_t SDNode::getAsZExtVal() const {
1652+
return cast<ConstantSDNode>(this)->getZExtValue();
1653+
}
1654+
16481655
const APInt &SDNode::getConstantOperandAPInt(unsigned Num) const {
16491656
return cast<ConstantSDNode>(getOperand(Num))->getAPIntValue();
16501657
}

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14713,7 +14713,7 @@ SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
1471314713

1471414714
SDValue EltNo = N0->getOperand(1);
1471514715
if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) {
14716-
int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
14716+
int Elt = EltNo->getAsZExtVal();
1471714717
int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1));
1471814718

1471914719
SDLoc DL(N);

‎llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -551,7 +551,7 @@ void InstrEmitter::EmitSubregNode(SDNode *Node,
551551
SDValue N0 = Node->getOperand(0);
552552
SDValue N1 = Node->getOperand(1);
553553
SDValue N2 = Node->getOperand(2);
554-
unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
554+
unsigned SubIdx = N2->getAsZExtVal();
555555

556556
// Figure out the register class to create for the destreg. It should be
557557
// the largest legal register class supporting SubIdx sub-registers.
@@ -650,7 +650,7 @@ void InstrEmitter::EmitRegSequence(SDNode *Node,
650650
// Skip physical registers as they don't have a vreg to get and we'll
651651
// insert copies for them in TwoAddressInstructionPass anyway.
652652
if (!R || !R->getReg().isPhysical()) {
653-
unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
653+
unsigned SubIdx = Op->getAsZExtVal();
654654
unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
655655
const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
656656
const TargetRegisterClass *SRC =

‎llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2511,7 +2511,7 @@ SDValue DAGTypeLegalizer::PromoteFloatRes_EXTRACT_VECTOR_ELT(SDNode *N) {
25112511
EVT VecVT = Vec->getValueType(0);
25122512
EVT EltVT = VecVT.getVectorElementType();
25132513

2514-
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2514+
uint64_t IdxVal = Idx->getAsZExtVal();
25152515

25162516
switch (getTypeAction(VecVT)) {
25172517
default: break;

‎llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5570,7 +5570,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
55705570
getTypeAction(InVT) == TargetLowering::TypeLegal) {
55715571
EVT NInVT = InVT.getHalfNumVectorElementsVT(*DAG.getContext());
55725572
unsigned NElts = NInVT.getVectorMinNumElements();
5573-
uint64_t IdxVal = cast<ConstantSDNode>(BaseIdx)->getZExtValue();
5573+
uint64_t IdxVal = BaseIdx->getAsZExtVal();
55745574

55755575
SDValue Step1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NInVT, InOp0,
55765576
DAG.getConstant(alignDown(IdxVal, NElts), dl,

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1442,7 +1442,7 @@ void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
14421442
std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
14431443

14441444
Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
1445-
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1445+
uint64_t IdxVal = Idx->getAsZExtVal();
14461446
Hi = DAG.getNode(
14471447
ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
14481448
DAG.getVectorIdxConstant(IdxVal + LoVT.getVectorMinNumElements(), dl));
@@ -1466,7 +1466,7 @@ void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
14661466
// If we know the index is in the first half, and we know the subvector
14671467
// doesn't cross the boundary between the halves, we can avoid spilling the
14681468
// vector, and insert into the lower half of the split vector directly.
1469-
unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1469+
unsigned IdxVal = Idx->getAsZExtVal();
14701470
if (IdxVal + SubElems <= LoElems) {
14711471
Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx);
14721472
return;
@@ -3279,7 +3279,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_INSERT_SUBVECTOR(SDNode *N,
32793279
SDValue Lo, Hi;
32803280
GetSplitVector(SubVec, Lo, Hi);
32813281

3282-
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
3282+
uint64_t IdxVal = Idx->getAsZExtVal();
32833283
uint64_t LoElts = Lo.getValueType().getVectorMinNumElements();
32843284

32853285
SDValue FirstInsertion =
@@ -3301,7 +3301,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
33013301
GetSplitVector(N->getOperand(0), Lo, Hi);
33023302

33033303
uint64_t LoEltsMin = Lo.getValueType().getVectorMinNumElements();
3304-
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
3304+
uint64_t IdxVal = Idx->getAsZExtVal();
33053305

33063306
if (IdxVal < LoEltsMin) {
33073307
assert(IdxVal + SubVT.getVectorMinNumElements() <= LoEltsMin &&
@@ -5257,7 +5257,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
52575257
EVT InVT = InOp.getValueType();
52585258

52595259
// Check if we can just return the input vector after widening.
5260-
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
5260+
uint64_t IdxVal = Idx->getAsZExtVal();
52615261
if (IdxVal == 0 && InVT == WidenVT)
52625262
return InOp;
52635263

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7197,8 +7197,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
71977197
assert(isa<ConstantSDNode>(N3) &&
71987198
"Insert subvector index must be constant");
71997199
assert((VT.isScalableVector() != N2VT.isScalableVector() ||
7200-
(N2VT.getVectorMinNumElements() +
7201-
cast<ConstantSDNode>(N3)->getZExtValue()) <=
7200+
(N2VT.getVectorMinNumElements() + N3->getAsZExtVal()) <=
72027201
VT.getVectorMinNumElements()) &&
72037202
"Insert subvector overflow!");
72047203
assert(cast<ConstantSDNode>(N3)->getAPIntValue().getBitWidth() ==
@@ -9986,8 +9985,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
99869985
Ops[1].getValueType().isFloatingPoint() &&
99879986
VTList.VTs[0].bitsLT(Ops[1].getValueType()) &&
99889987
isa<ConstantSDNode>(Ops[2]) &&
9989-
(cast<ConstantSDNode>(Ops[2])->getZExtValue() == 0 ||
9990-
cast<ConstantSDNode>(Ops[2])->getZExtValue() == 1) &&
9988+
(Ops[2]->getAsZExtVal() == 0 || Ops[2]->getAsZExtVal() == 1) &&
99919989
"Invalid STRICT_FP_ROUND!");
99929990
break;
99939991
#if 0

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 13 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -5644,7 +5644,7 @@ static SDValue expandDivFix(unsigned Opcode, const SDLoc &DL,
56445644
// expansion/promotion) if it was possible to expand a libcall of an
56455645
// illegal type during operation legalization. But it's not, so things
56465646
// get a bit hacky.
5647-
unsigned ScaleInt = cast<ConstantSDNode>(Scale)->getZExtValue();
5647+
unsigned ScaleInt = Scale->getAsZExtVal();
56485648
if ((ScaleInt > 0 || (Saturating && Signed)) &&
56495649
(TLI.isTypeLegal(VT) ||
56505650
(VT.isVector() && TLI.isTypeLegal(VT.getVectorElementType())))) {
@@ -7657,8 +7657,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
76577657
// suitable for the target. Convert the index as required.
76587658
MVT VectorIdxTy = TLI.getVectorIdxTy(DAG.getDataLayout());
76597659
if (Index.getValueType() != VectorIdxTy)
7660-
Index = DAG.getVectorIdxConstant(
7661-
cast<ConstantSDNode>(Index)->getZExtValue(), sdl);
7660+
Index = DAG.getVectorIdxConstant(Index->getAsZExtVal(), sdl);
76627661

76637662
EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
76647663
setValue(&I, DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, ResultVT, Vec, SubVec,
@@ -7674,8 +7673,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
76747673
// suitable for the target. Convert the index as required.
76757674
MVT VectorIdxTy = TLI.getVectorIdxTy(DAG.getDataLayout());
76767675
if (Index.getValueType() != VectorIdxTy)
7677-
Index = DAG.getVectorIdxConstant(
7678-
cast<ConstantSDNode>(Index)->getZExtValue(), sdl);
7676+
Index = DAG.getVectorIdxConstant(Index->getAsZExtVal(), sdl);
76797677

76807678
setValue(&I,
76817679
DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, ResultVT, Vec, Index));
@@ -8138,7 +8136,7 @@ void SelectionDAGBuilder::visitVectorPredicationIntrinsic(
81388136
case ISD::VP_IS_FPCLASS: {
81398137
const DataLayout DLayout = DAG.getDataLayout();
81408138
EVT DestVT = TLI.getValueType(DLayout, VPIntrin.getType());
8141-
auto Constant = cast<ConstantSDNode>(OpValues[1])->getZExtValue();
8139+
auto Constant = OpValues[1]->getAsZExtVal();
81428140
SDValue Check = DAG.getTargetConstant(Constant, DL, MVT::i32);
81438141
SDValue V = DAG.getNode(ISD::VP_IS_FPCLASS, DL, DestVT,
81448142
{OpValues[0], Check, OpValues[2], OpValues[3]});
@@ -9175,8 +9173,7 @@ findMatchingInlineAsmOperand(unsigned OperandNo,
91759173
unsigned CurOp = InlineAsm::Op_FirstOperand;
91769174
for (; OperandNo; --OperandNo) {
91779175
// Advance to the next operand.
9178-
unsigned OpFlag =
9179-
cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
9176+
unsigned OpFlag = AsmNodeOperands[CurOp]->getAsZExtVal();
91809177
const InlineAsm::Flag F(OpFlag);
91819178
assert(
91829179
(F.isRegDefKind() || F.isRegDefEarlyClobberKind() || F.isMemKind()) &&
@@ -9482,8 +9479,7 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
94829479
// just use its register.
94839480
auto CurOp = findMatchingInlineAsmOperand(OpInfo.getMatchedOperand(),
94849481
AsmNodeOperands);
9485-
InlineAsm::Flag Flag(
9486-
cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue());
9482+
InlineAsm::Flag Flag(AsmNodeOperands[CurOp]->getAsZExtVal());
94879483
if (Flag.isRegDefKind() || Flag.isRegDefEarlyClobberKind()) {
94889484
if (OpInfo.isIndirect) {
94899485
// This happens on gcc/testsuite/gcc.dg/pr8788-1.c
@@ -9987,14 +9983,14 @@ void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
99879983
// constant nodes.
99889984
SDValue ID = getValue(CI.getArgOperand(0));
99899985
assert(ID.getValueType() == MVT::i64);
9990-
SDValue IDConst = DAG.getTargetConstant(
9991-
cast<ConstantSDNode>(ID)->getZExtValue(), DL, ID.getValueType());
9986+
SDValue IDConst =
9987+
DAG.getTargetConstant(ID->getAsZExtVal(), DL, ID.getValueType());
99929988
Ops.push_back(IDConst);
99939989

99949990
SDValue Shad = getValue(CI.getArgOperand(1));
99959991
assert(Shad.getValueType() == MVT::i32);
9996-
SDValue ShadConst = DAG.getTargetConstant(
9997-
cast<ConstantSDNode>(Shad)->getZExtValue(), DL, Shad.getValueType());
9992+
SDValue ShadConst =
9993+
DAG.getTargetConstant(Shad->getAsZExtVal(), DL, Shad.getValueType());
99989994
Ops.push_back(ShadConst);
99999995

100009996
// Add the live variables.
@@ -10043,7 +10039,7 @@ void SelectionDAGBuilder::visitPatchpoint(const CallBase &CB,
1004310039

1004410040
// Get the real number of arguments participating in the call <numArgs>
1004510041
SDValue NArgVal = getValue(CB.getArgOperand(PatchPointOpers::NArgPos));
10046-
unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
10042+
unsigned NumArgs = NArgVal->getAsZExtVal();
1004710043

1004810044
// Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
1004910045
// Intrinsics include all meta-operands up to but not including CC.
@@ -10090,12 +10086,9 @@ void SelectionDAGBuilder::visitPatchpoint(const CallBase &CB,
1009010086

1009110087
// Add the <id> and <numBytes> constants.
1009210088
SDValue IDVal = getValue(CB.getArgOperand(PatchPointOpers::IDPos));
10093-
Ops.push_back(DAG.getTargetConstant(
10094-
cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
10089+
Ops.push_back(DAG.getTargetConstant(IDVal->getAsZExtVal(), dl, MVT::i64));
1009510090
SDValue NBytesVal = getValue(CB.getArgOperand(PatchPointOpers::NBytesPos));
10096-
Ops.push_back(DAG.getTargetConstant(
10097-
cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
10098-
MVT::i32));
10091+
Ops.push_back(DAG.getTargetConstant(NBytesVal->getAsZExtVal(), dl, MVT::i32));
1009910092

1010010093
// Add the callee.
1010110094
Ops.push_back(Callee);

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -149,7 +149,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
149149
case ISD::INTRINSIC_VOID:
150150
case ISD::INTRINSIC_W_CHAIN: {
151151
unsigned OpNo = getOpcode() == ISD::INTRINSIC_WO_CHAIN ? 0 : 1;
152-
unsigned IID = cast<ConstantSDNode>(getOperand(OpNo))->getZExtValue();
152+
unsigned IID = getOperand(OpNo)->getAsZExtVal();
153153
if (IID < Intrinsic::num_intrinsics)
154154
return Intrinsic::getBaseName((Intrinsic::ID)IID).str();
155155
if (!G)

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Lines changed: 6 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2125,7 +2125,7 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
21252125
--e; // Don't process a glue operand if it is here.
21262126

21272127
while (i != e) {
2128-
InlineAsm::Flag Flags(cast<ConstantSDNode>(InOps[i])->getZExtValue());
2128+
InlineAsm::Flag Flags(InOps[i]->getAsZExtVal());
21292129
if (!Flags.isMemKind() && !Flags.isFuncKind()) {
21302130
// Just skip over this operand, copying the operands verbatim.
21312131
Ops.insert(Ops.end(), InOps.begin() + i,
@@ -2139,12 +2139,10 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
21392139
if (Flags.isUseOperandTiedToDef(TiedToOperand)) {
21402140
// We need the constraint ID from the operand this is tied to.
21412141
unsigned CurOp = InlineAsm::Op_FirstOperand;
2142-
Flags =
2143-
InlineAsm::Flag(cast<ConstantSDNode>(InOps[CurOp])->getZExtValue());
2142+
Flags = InlineAsm::Flag(InOps[CurOp]->getAsZExtVal());
21442143
for (; TiedToOperand; --TiedToOperand) {
21452144
CurOp += Flags.getNumOperandRegisters() + 1;
2146-
Flags = InlineAsm::Flag(
2147-
cast<ConstantSDNode>(InOps[CurOp])->getZExtValue());
2145+
Flags = InlineAsm::Flag(InOps[CurOp]->getAsZExtVal());
21482146
}
21492147
}
21502148

@@ -2384,9 +2382,8 @@ void SelectionDAGISel::pushStackMapLiveVariable(SmallVectorImpl<SDValue> &Ops,
23842382
if (OpNode->getOpcode() == ISD::Constant) {
23852383
Ops.push_back(
23862384
CurDAG->getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
2387-
Ops.push_back(
2388-
CurDAG->getTargetConstant(cast<ConstantSDNode>(OpNode)->getZExtValue(),
2389-
DL, OpVal.getValueType()));
2385+
Ops.push_back(CurDAG->getTargetConstant(OpNode->getAsZExtVal(), DL,
2386+
OpVal.getValueType()));
23902387
} else {
23912388
Ops.push_back(OpVal);
23922389
}
@@ -2456,7 +2453,7 @@ void SelectionDAGISel::Select_PATCHPOINT(SDNode *N) {
24562453
Ops.push_back(*It++);
24572454

24582455
// Push the args for the call.
2459-
for (uint64_t I = cast<ConstantSDNode>(NumArgs)->getZExtValue(); I != 0; I--)
2456+
for (uint64_t I = NumArgs->getAsZExtVal(); I != 0; I--)
24602457
Ops.push_back(*It++);
24612458

24622459
// Now push the live variables.

‎llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -580,7 +580,7 @@ bool AArch64DAGToDAGISel::SelectArithImmed(SDValue N, SDValue &Val,
580580
if (!isa<ConstantSDNode>(N.getNode()))
581581
return false;
582582

583-
uint64_t Immed = cast<ConstantSDNode>(N.getNode())->getZExtValue();
583+
uint64_t Immed = N.getNode()->getAsZExtVal();
584584
unsigned ShiftAmt;
585585

586586
if (Immed >> 12 == 0) {
@@ -611,7 +611,7 @@ bool AArch64DAGToDAGISel::SelectNegArithImmed(SDValue N, SDValue &Val,
611611
return false;
612612

613613
// The immediate operand must be a 24-bit zero-extended immediate.
614-
uint64_t Immed = cast<ConstantSDNode>(N.getNode())->getZExtValue();
614+
uint64_t Immed = N.getNode()->getAsZExtVal();
615615

616616
// This negation is almost always valid, but "cmp wN, #0" and "cmn wN, #0"
617617
// have the opposite effect on the C flag, so this pattern mustn't match under
@@ -1326,7 +1326,7 @@ bool AArch64DAGToDAGISel::SelectAddrModeXRO(SDValue N, unsigned Size,
13261326
// MOV X0, WideImmediate
13271327
// LDR X2, [BaseReg, X0]
13281328
if (isa<ConstantSDNode>(RHS)) {
1329-
int64_t ImmOff = (int64_t)cast<ConstantSDNode>(RHS)->getZExtValue();
1329+
int64_t ImmOff = (int64_t)RHS->getAsZExtVal();
13301330
// Skip the immediate can be selected by load/store addressing mode.
13311331
// Also skip the immediate can be encoded by a single ADD (SUB is also
13321332
// checked by using -ImmOff).

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -3588,8 +3588,7 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
35883588
// cmp w13, w12
35893589
// can be turned into:
35903590
// cmp w12, w11, lsl #1
3591-
if (!isa<ConstantSDNode>(RHS) ||
3592-
!isLegalArithImmed(cast<ConstantSDNode>(RHS)->getZExtValue())) {
3591+
if (!isa<ConstantSDNode>(RHS) || !isLegalArithImmed(RHS->getAsZExtVal())) {
35933592
SDValue TheLHS = isCMN(LHS, CC) ? LHS.getOperand(1) : LHS;
35943593

35953594
if (getCmpOperandFoldingProfit(TheLHS) > getCmpOperandFoldingProfit(RHS)) {
@@ -3623,7 +3622,7 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
36233622
cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
36243623
cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
36253624
LHS.getNode()->hasNUsesOfValue(1, 0)) {
3626-
int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
3625+
int16_t ValueofRHS = RHS->getAsZExtVal();
36273626
if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
36283627
SDValue SExt =
36293628
DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
@@ -5619,7 +5618,7 @@ SDValue AArch64TargetLowering::LowerMGATHER(SDValue Op,
56195618

56205619
// SVE supports an index scaled by sizeof(MemVT.elt) only, everything else
56215620
// must be calculated before hand.
5622-
uint64_t ScaleVal = cast<ConstantSDNode>(Scale)->getZExtValue();
5621+
uint64_t ScaleVal = Scale->getAsZExtVal();
56235622
if (IsScaled && ScaleVal != MemVT.getScalarStoreSize()) {
56245623
assert(isPowerOf2_64(ScaleVal) && "Expecting power-of-two types");
56255624
EVT IndexVT = Index.getValueType();
@@ -5707,7 +5706,7 @@ SDValue AArch64TargetLowering::LowerMSCATTER(SDValue Op,
57075706

57085707
// SVE supports an index scaled by sizeof(MemVT.elt) only, everything else
57095708
// must be calculated before hand.
5710-
uint64_t ScaleVal = cast<ConstantSDNode>(Scale)->getZExtValue();
5709+
uint64_t ScaleVal = Scale->getAsZExtVal();
57115710
if (IsScaled && ScaleVal != MemVT.getScalarStoreSize()) {
57125711
assert(isPowerOf2_64(ScaleVal) && "Expecting power-of-two types");
57135712
EVT IndexVT = Index.getValueType();
@@ -22011,7 +22010,7 @@ static SDValue performBRCONDCombine(SDNode *N,
2201122010
SDValue Cmp = N->getOperand(3);
2201222011

2201322012
assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
22014-
unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
22013+
unsigned CC = CCVal->getAsZExtVal();
2201522014
if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
2201622015
return SDValue();
2201722016

‎llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -172,7 +172,7 @@ static SDValue EmitUnrolledSetTag(SelectionDAG &DAG, const SDLoc &dl,
172172
SDValue AArch64SelectionDAGInfo::EmitTargetCodeForSetTag(
173173
SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Addr,
174174
SDValue Size, MachinePointerInfo DstPtrInfo, bool ZeroData) const {
175-
uint64_t ObjSize = cast<ConstantSDNode>(Size)->getZExtValue();
175+
uint64_t ObjSize = Size->getAsZExtVal();
176176
assert(ObjSize % 16 == 0);
177177

178178
MachineFunction &MF = DAG.getMachineFunction();

‎llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -373,7 +373,7 @@ const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
373373
Subtarget->getRegisterInfo()->getRegClass(RCID);
374374

375375
SDValue SubRegOp = N->getOperand(OpNo + 1);
376-
unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue();
376+
unsigned SubRegIdx = SubRegOp->getAsZExtVal();
377377
return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC,
378378
SubRegIdx);
379379
}

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