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[RISCV] Add tests for fixed-length vwadd[u].{w,v}v with disjoint or. NFC
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll

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@@ -876,3 +876,107 @@ define <2 x i64> @vwadd_v2i64_of_v2i16(ptr %x, ptr %y) {
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%e = add <2 x i64> %c, %d
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ret <2 x i64> %e
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}
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; %x.i32 and %y.i32 are disjoint, so DAGCombiner will combine it into an or.
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define <4 x i32> @vwaddu_vv_disjoint_or_add(<4 x i8> %x.i8, <4 x i8> %y.i8) {
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; CHECK-LABEL: vwaddu_vv_disjoint_or_add:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; CHECK-NEXT: vzext.vf2 v10, v8
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; CHECK-NEXT: vsll.vi v8, v10, 8
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; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; CHECK-NEXT: vzext.vf2 v10, v8
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; CHECK-NEXT: vzext.vf4 v8, v9
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; CHECK-NEXT: vor.vv v8, v10, v8
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; CHECK-NEXT: ret
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%x.i16 = zext <4 x i8> %x.i8 to <4 x i16>
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%x.shl = shl <4 x i16> %x.i16, splat (i16 8)
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%x.i32 = zext <4 x i16> %x.shl to <4 x i32>
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%y.i32 = zext <4 x i8> %y.i8 to <4 x i32>
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%add = add <4 x i32> %x.i32, %y.i32
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ret <4 x i32> %add
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}
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define <4 x i32> @vwaddu_vv_disjoint_or(<4 x i16> %x.i16, <4 x i16> %y.i16) {
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; CHECK-LABEL: vwaddu_vv_disjoint_or:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; CHECK-NEXT: vor.vv v9, v8, v9
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; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; CHECK-NEXT: vzext.vf2 v8, v9
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; CHECK-NEXT: ret
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%x.i32 = zext <4 x i16> %x.i16 to <4 x i32>
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%y.i32 = zext <4 x i16> %y.i16 to <4 x i32>
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%or = or disjoint <4 x i32> %x.i32, %y.i32
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ret <4 x i32> %or
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}
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define <4 x i32> @vwadd_vv_disjoint_or(<4 x i16> %x.i16, <4 x i16> %y.i16) {
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; CHECK-LABEL: vwadd_vv_disjoint_or:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; CHECK-NEXT: vor.vv v9, v8, v9
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; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; CHECK-NEXT: vsext.vf2 v8, v9
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; CHECK-NEXT: ret
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%x.i32 = sext <4 x i16> %x.i16 to <4 x i32>
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%y.i32 = sext <4 x i16> %y.i16 to <4 x i32>
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%or = or disjoint <4 x i32> %x.i32, %y.i32
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ret <4 x i32> %or
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}
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define <4 x i32> @vwaddu_vx_disjoint_or(<4 x i16> %x.i16, i16 %y.i16) {
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; CHECK-LABEL: vwaddu_vx_disjoint_or:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; CHECK-NEXT: vor.vx v9, v8, a0
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; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; CHECK-NEXT: vzext.vf2 v8, v9
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; CHECK-NEXT: ret
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%x.i32 = zext <4 x i16> %x.i16 to <4 x i32>
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%y.head = insertelement <4 x i16> poison, i16 %y.i16, i32 0
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%y.splat = shufflevector <4 x i16> %y.head, <4 x i16> poison, <4 x i32> zeroinitializer
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%y.i32 = zext <4 x i16> %y.splat to <4 x i32>
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%or = or disjoint <4 x i32> %x.i32, %y.i32
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ret <4 x i32> %or
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}
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define <4 x i32> @vwadd_vx_disjoint_or(<4 x i16> %x.i16, i16 %y.i16) {
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; CHECK-LABEL: vwadd_vx_disjoint_or:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; CHECK-NEXT: vor.vx v9, v8, a0
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; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; CHECK-NEXT: vsext.vf2 v8, v9
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; CHECK-NEXT: ret
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%x.i32 = sext <4 x i16> %x.i16 to <4 x i32>
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%y.head = insertelement <4 x i16> poison, i16 %y.i16, i32 0
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%y.splat = shufflevector <4 x i16> %y.head, <4 x i16> poison, <4 x i32> zeroinitializer
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%y.i32 = sext <4 x i16> %y.splat to <4 x i32>
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%or = or disjoint <4 x i32> %x.i32, %y.i32
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ret <4 x i32> %or
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}
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define <4 x i32> @vwaddu_wv_disjoint_or(<4 x i32> %x.i32, <4 x i16> %y.i16) {
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; CHECK-LABEL: vwaddu_wv_disjoint_or:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vzext.vf2 v10, v9
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; CHECK-NEXT: vor.vv v8, v8, v10
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; CHECK-NEXT: ret
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%y.i32 = zext <4 x i16> %y.i16 to <4 x i32>
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%or = or disjoint <4 x i32> %x.i32, %y.i32
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ret <4 x i32> %or
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}
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define <4 x i32> @vwadd_wv_disjoint_or(<4 x i32> %x.i32, <4 x i16> %y.i16) {
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; CHECK-LABEL: vwadd_wv_disjoint_or:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vsext.vf2 v10, v9
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; CHECK-NEXT: vor.vv v8, v8, v10
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; CHECK-NEXT: ret
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%y.i32 = sext <4 x i16> %y.i16 to <4 x i32>
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%or = or disjoint <4 x i32> %x.i32, %y.i32
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ret <4 x i32> %or
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}

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