@@ -6285,7 +6285,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
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Flags.setNonNeg(N1->getFlags().hasNonNeg());
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return getNode(OpOpcode, DL, VT, N1.getOperand(0), Flags);
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}
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- if (OpOpcode == ISD::UNDEF )
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+ if (N1.isUndef() )
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// sext(undef) = 0, because the top bits will all be the same.
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return getConstant(0, DL, VT);
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break;
@@ -6305,7 +6305,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
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Flags.setNonNeg(N1->getFlags().hasNonNeg());
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return getNode(ISD::ZERO_EXTEND, DL, VT, N1.getOperand(0), Flags);
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}
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- if (OpOpcode == ISD::UNDEF )
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+ if (N1.isUndef() )
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// zext(undef) = 0, because the top bits will be zero.
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return getConstant(0, DL, VT);
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@@ -6347,7 +6347,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
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// (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x)
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return getNode(OpOpcode, DL, VT, N1.getOperand(0), Flags);
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}
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- if (OpOpcode == ISD::UNDEF )
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+ if (N1.isUndef() )
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return getUNDEF(VT);
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// (ext (trunc x)) -> x
@@ -6382,7 +6382,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
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return getNode(ISD::TRUNCATE, DL, VT, N1.getOperand(0));
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return N1.getOperand(0);
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}
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- if (OpOpcode == ISD::UNDEF )
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+ if (N1.isUndef() )
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return getUNDEF(VT);
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if (OpOpcode == ISD::VSCALE && !NewNodesMustHaveLegalTypes)
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return getVScale(DL, VT,
@@ -6400,22 +6400,22 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
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break;
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case ISD::ABS:
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assert(VT.isInteger() && VT == N1.getValueType() && "Invalid ABS!");
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- if (OpOpcode == ISD::UNDEF )
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+ if (N1.isUndef() )
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return getConstant(0, DL, VT);
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break;
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case ISD::BSWAP:
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assert(VT.isInteger() && VT == N1.getValueType() && "Invalid BSWAP!");
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assert((VT.getScalarSizeInBits() % 16 == 0) &&
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"BSWAP types must be a multiple of 16 bits!");
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- if (OpOpcode == ISD::UNDEF )
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+ if (N1.isUndef() )
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return getUNDEF(VT);
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// bswap(bswap(X)) -> X.
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if (OpOpcode == ISD::BSWAP)
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return N1.getOperand(0);
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break;
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case ISD::BITREVERSE:
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assert(VT.isInteger() && VT == N1.getValueType() && "Invalid BITREVERSE!");
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- if (OpOpcode == ISD::UNDEF )
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+ if (N1.isUndef() )
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return getUNDEF(VT);
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break;
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case ISD::BITCAST:
@@ -6424,7 +6424,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
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if (VT == N1.getValueType()) return N1; // noop conversion.
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if (OpOpcode == ISD::BITCAST) // bitconv(bitconv(x)) -> bitconv(x)
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return getNode(ISD::BITCAST, DL, VT, N1.getOperand(0));
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- if (OpOpcode == ISD::UNDEF )
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+ if (N1.isUndef() )
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return getUNDEF(VT);
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break;
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case ISD::SCALAR_TO_VECTOR:
@@ -6434,7 +6434,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
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N1.getValueType().isInteger() &&
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VT.getVectorElementType().bitsLE(N1.getValueType()))) &&
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"Illegal SCALAR_TO_VECTOR node!");
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- if (OpOpcode == ISD::UNDEF )
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+ if (N1.isUndef() )
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return getUNDEF(VT);
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// scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined.
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if (OpOpcode == ISD::EXTRACT_VECTOR_ELT &&
@@ -6445,7 +6445,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
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break;
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case ISD::FNEG:
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// Negation of an unknown bag of bits is still completely undefined.
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- if (OpOpcode == ISD::UNDEF )
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+ if (N1.isUndef() )
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return getUNDEF(VT);
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if (OpOpcode == ISD::FNEG) // --X -> X
@@ -13364,7 +13364,7 @@ void BuildVectorSDNode::recastRawBits(bool IsLittleEndian,
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bool BuildVectorSDNode::isConstant() const {
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for (const SDValue &Op : op_values()) {
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unsigned Opc = Op.getOpcode();
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- if (Opc != ISD::UNDEF && Opc != ISD::Constant && Opc != ISD::ConstantFP)
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+ if (!Op.isUndef() && Opc != ISD::Constant && Opc != ISD::ConstantFP)
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return false;
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}
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return true;
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