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[VP] IR expansion for inttoptr/ptrtoint
Add basic handling for VP ops that can expand to cast intrinsics Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D159478
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‎llvm/lib/CodeGen/ExpandVectorPredication.cpp

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Original file line numberDiff line numberDiff line change
@@ -179,6 +179,10 @@ struct CachingVPExpander {
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Value *expandPredicationInReduction(IRBuilder<> &Builder,
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VPReductionIntrinsic &PI);
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/// Lower this VP cast operation to a non-VP intrinsic.
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Value *expandPredicationToCastIntrinsic(IRBuilder<> &Builder,
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VPIntrinsic &VPI);
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/// Lower this VP memory operation to a non-VP intrinsic.
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Value *expandPredicationInMemoryIntrinsic(IRBuilder<> &Builder,
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VPIntrinsic &VPI);
@@ -436,6 +440,27 @@ CachingVPExpander::expandPredicationInReduction(IRBuilder<> &Builder,
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return Reduction;
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}
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Value *CachingVPExpander::expandPredicationToCastIntrinsic(IRBuilder<> &Builder,
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VPIntrinsic &VPI) {
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// TODO: Add anthor Cast Intrinsic, VP_TRUNC/VP_ZEXT
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switch (VPI.getIntrinsicID()) {
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default:
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llvm_unreachable("Not a VP memory intrinsic");
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case Intrinsic::vp_inttoptr: {
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Value *NewOp =
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Builder.CreateIntToPtr(VPI.getOperand(0), VPI.getType(), VPI.getName());
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replaceOperation(*NewOp, VPI);
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return NewOp;
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}
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case Intrinsic::vp_ptrtoint: {
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Value *NewOp =
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Builder.CreatePtrToInt(VPI.getOperand(0), VPI.getType(), VPI.getName());
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replaceOperation(*NewOp, VPI);
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return NewOp;
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}
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}
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}
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Value *
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CachingVPExpander::expandPredicationInMemoryIntrinsic(IRBuilder<> &Builder,
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VPIntrinsic &VPI) {
@@ -598,6 +623,10 @@ Value *CachingVPExpander::expandPredication(VPIntrinsic &VPI) {
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if (auto *VPCmp = dyn_cast<VPCmpIntrinsic>(&VPI))
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return expandPredicationInComparison(Builder, *VPCmp);
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if (VPCastIntrinsic::isVPCast(VPI.getIntrinsicID())) {
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return expandPredicationToCastIntrinsic(Builder, VPI);
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}
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switch (VPI.getIntrinsicID()) {
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default:
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break;

‎llvm/test/CodeGen/X86/expand-vp-cast-intrinsics.ll

Lines changed: 119 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,119 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=X86
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl | FileCheck %s --check-prefixes=AVX,AVX512
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declare <4 x ptr> @llvm.vp.inttoptr.v4p0.v4i32(<4 x i32>, <4 x i1>, i32)
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define <4 x ptr> @inttoptr_v4p0_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
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; X86-LABEL: inttoptr_v4p0_v4i32:
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; X86: # %bb.0:
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; X86-NEXT: retl
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;
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; SSE-LABEL: inttoptr_v4p0_v4i32:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm0, %xmm1
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; SSE-NEXT: xorps %xmm2, %xmm2
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; SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
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; SSE-NEXT: unpckhps {{.*#+}} xmm1 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: inttoptr_v4p0_v4i32:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm1 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
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; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: inttoptr_v4p0_v4i32:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: inttoptr_v4p0_v4i32:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
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; AVX512-NEXT: retq
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%v = call <4 x ptr> @llvm.vp.inttoptr.v4p0.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl)
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ret <4 x ptr> %v
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}
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declare <4 x ptr> @llvm.vp.inttoptr.v4p0.v4i64(<4 x i64>, <4 x i1>, i32)
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define <4 x ptr> @inttoptr_v4p0_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
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; X86-LABEL: inttoptr_v4p0_v4i64:
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; X86: # %bb.0:
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; X86-NEXT: vextractf128 $1, %ymm0, %xmm1
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; X86-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
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; X86-NEXT: vzeroupper
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; X86-NEXT: retl
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;
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; SSE-LABEL: inttoptr_v4p0_v4i64:
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; SSE: # %bb.0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: inttoptr_v4p0_v4i64:
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; AVX: # %bb.0:
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; AVX-NEXT: retq
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%v = call <4 x ptr> @llvm.vp.inttoptr.v4p0.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl)
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ret <4 x ptr> %v
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}
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declare <4 x i32> @llvm.vp.ptrtoint.v4i32.v4p0(<4 x ptr>, <4 x i1>, i32)
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define <4 x i32> @ptrtoint_v4i32_v4p0(<4 x ptr> %va, <4 x i1> %m, i32 zeroext %evl) {
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; X86-LABEL: ptrtoint_v4i32_v4p0:
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; X86: # %bb.0:
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; X86-NEXT: retl
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;
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; SSE-LABEL: ptrtoint_v4i32_v4p0:
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; SSE: # %bb.0:
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; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: ptrtoint_v4i32_v4p0:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
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; AVX1-NEXT: vzeroupper
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: ptrtoint_v4i32_v4p0:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
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; AVX2-NEXT: vzeroupper
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: ptrtoint_v4i32_v4p0:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpmovqd %ymm0, %xmm0
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; AVX512-NEXT: vzeroupper
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; AVX512-NEXT: retq
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%v = call <4 x i32> @llvm.vp.ptrtoint.v4i32.v4p0(<4 x ptr> %va, <4 x i1> %m, i32 %evl)
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ret <4 x i32> %v
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}
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declare <4 x i64> @llvm.vp.ptrtoint.v4i64.v4p0(<4 x ptr>, <4 x i1>, i32)
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define <4 x i64> @ptrtoint_v4i64_v4p0(<4 x ptr> %va, <4 x i1> %m, i32 zeroext %evl) {
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; X86-LABEL: ptrtoint_v4i64_v4p0:
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; X86: # %bb.0:
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; X86-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; X86-NEXT: vpunpckhdq {{.*#+}} xmm1 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
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; X86-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
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; X86-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; X86-NEXT: retl
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;
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; SSE-LABEL: ptrtoint_v4i64_v4p0:
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; SSE: # %bb.0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: ptrtoint_v4i64_v4p0:
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; AVX: # %bb.0:
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; AVX-NEXT: retq
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%v = call <4 x i64> @llvm.vp.ptrtoint.v4i64.v4p0(<4 x ptr> %va, <4 x i1> %m, i32 %evl)
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ret <4 x i64> %v
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}

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