Revert Add host-supports-nvptx requirement to lit tests (#66102 and #66129) (#66225)

Author: frgossen

mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/dump-ptx.mlir

@@ -1,5 +1,3 @@
-// REQUIRES: host-supports-nvptx
-
 // RUN: mlir-opt %s \
 // RUN: | mlir-opt -test-lower-to-nvvm -debug-only=serialize-to-isa \
 // RUN: 2>&1 | FileCheck %s

mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-matvec-const.mlir

@@ -1,4 +1,3 @@
-// REQUIRES: host-supports-nvptx
 //
 // NOTE: this test requires gpu-sm80
 //

mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-matvec.mlir

@@ -1,4 +1,3 @@
-// REQUIRES: host-supports-nvptx
 //
 // NOTE: this test requires gpu-sm80
 //

mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-mma-2-4-f16.mlir

@@ -1,5 +1,3 @@
-// REQUIRES: host-supports-nvptx
-
 //
 // NOTE: this test requires gpu-sm80
 //

mlir/test/Integration/Dialect/Vector/GPU/CUDA/test-reduction-distribute.mlir

@@ -1,5 +1,3 @@
-// REQUIRES: host-supports-nvptx
-
 // RUN: mlir-opt %s -test-vector-warp-distribute="hoist-uniform distribute-transfer-write propagate-distribution" -canonicalize |\
 // RUN: mlir-opt -test-vector-warp-distribute=rewrite-warp-ops-to-scf-if |\
 // RUN: mlir-opt -lower-affine -convert-vector-to-scf -convert-scf-to-cf -convert-vector-to-llvm \

mlir/test/Integration/Dialect/Vector/GPU/CUDA/test-warp-distribute.mlir

@@ -1,5 +1,3 @@
-// REQUIRES: host-supports-nvptx
-
 // Run the test cases without distributing ops to test default lowering. Run
 // everything on the same thread.
 // RUN: mlir-opt %s -test-vector-warp-distribute=rewrite-warp-ops-to-scf-if -canonicalize | \

mlir/test/Integration/GPU/CUDA/TensorCore/sm80/transform-mma-sync-matmul-f16-f16-accum.mlir

@@ -1,5 +1,3 @@
-// REQUIRES: host-supports-nvptx
-
 // RUN: mlir-opt %s \
 // RUN:  -test-transform-dialect-interpreter \
 // RUN:  -test-transform-dialect-erase-schedule \

mlir/test/Integration/GPU/CUDA/TensorCore/sm80/transform-mma-sync-matmul-f32.mlir

@@ -1,5 +1,3 @@
-// REQUIRES: host-supports-nvptx
-//
 // RUN: mlir-opt %s \
 // RUN:   -test-transform-dialect-interpreter \
 // RUN: | FileCheck %s --check-prefix=CHECK-MMA-SYNC

mlir/test/Integration/GPU/CUDA/TensorCore/wmma-matmul-f16.mlir

@@ -1,5 +1,3 @@
-// REQUIRES: host-supports-nvptx
-
 // RUN: mlir-opt %s \
 // RUN: | mlir-opt -test-lower-to-nvvm="cubin-chip=sm_70" \
 // RUN: | mlir-cpu-runner \

mlir/test/Integration/GPU/CUDA/TensorCore/wmma-matmul-f32-bare-ptr.mlir

@@ -1,5 +1,3 @@
-// REQUIRES: host-supports-nvptx
-
 // Tests memref bare pointer lowering convention both host side and kernel-side;
 // this works for only statically shaped memrefs.
 // Similar to the wmma-matmul-f32 but but with the memref bare pointer lowering convention.

mlir/test/Integration/GPU/CUDA/TensorCore/wmma-matmul-f32.mlir

@@ -1,5 +1,3 @@
-// REQUIRES: host-supports-nvptx
-
 // RUN: mlir-opt %s \
 // RUN: | mlir-opt -test-lower-to-nvvm="cubin-chip=sm_70" \
 // RUN: | mlir-cpu-runner \

mlir/test/Integration/GPU/CUDA/all-reduce-and.mlir

@@ -1,5 +1,3 @@
-// REQUIRES: host-supports-nvptx
-
 // RUN: mlir-opt %s \
 // RUN: | mlir-opt -test-lower-to-nvvm \
 // RUN: | mlir-cpu-runner \

mlir/test/Integration/GPU/CUDA/all-reduce-max.mlir

@@ -1,5 +1,3 @@
-// REQUIRES: host-supports-nvptx
-
 // RUN: mlir-opt %s \
 // RUN: | mlir-opt -test-lower-to-nvvm \
 // RUN: | mlir-cpu-runner \

mlir/test/Integration/GPU/CUDA/all-reduce-min.mlir

@@ -1,5 +1,3 @@
-// REQUIRES: host-supports-nvptx
-
 // RUN: mlir-opt %s \
 // RUN: | mlir-opt -test-lower-to-nvvm \
 // RUN: | mlir-cpu-runner \

mlir/test/Integration/GPU/CUDA/all-reduce-op.mlir

@@ -1,5 +1,3 @@
-// REQUIRES: host-supports-nvptx
-
 // RUN: mlir-opt %s \
 // RUN: | mlir-opt -test-lower-to-nvvm \
 // RUN: | mlir-cpu-runner \

mlir/test/Integration/GPU/CUDA/all-reduce-or.mlir

@@ -1,5 +1,3 @@
-// REQUIRES: host-supports-nvptx
-
 // RUN: mlir-opt %s \
 // RUN: | mlir-opt -test-lower-to-nvvm \
 // RUN: | mlir-cpu-runner \

mlir/test/Integration/GPU/CUDA/all-reduce-region.mlir

@@ -1,5 +1,3 @@
-// REQUIRES: host-supports-nvptx
-
 // RUN: mlir-opt %s \
 // RUN: | mlir-opt -test-lower-to-nvvm \
 // RUN: | mlir-cpu-runner \

mlir/test/Integration/GPU/CUDA/all-reduce-xor.mlir

@@ -1,5 +1,3 @@
-// REQUIRES: host-supports-nvptx
-
 // RUN: mlir-opt %s \
 // RUN: | mlir-opt -test-lower-to-nvvm \
 // RUN: | mlir-cpu-runner \

mlir/test/Integration/GPU/CUDA/async.mlir

@@ -1,5 +1,3 @@
-// REQUIRES: host-supports-nvptx
-
 // RUN: mlir-opt %s \
 // RUN: | mlir-opt -gpu-kernel-outlining \
 // RUN: | mlir-opt -pass-pipeline='builtin.module(gpu.module(strip-debuginfo,convert-gpu-to-nvvm),nvvm-attach-target)' \

mlir/test/Integration/GPU/CUDA/gpu-to-cubin.mlir

@@ -1,5 +1,3 @@
-// REQUIRES: host-supports-nvptx
-
 // RUN: mlir-opt %s \
 // RUN: | mlir-opt -test-lower-to-nvvm \
 // RUN: | mlir-cpu-runner \

mlir/test/Integration/GPU/CUDA/multiple-all-reduce.mlir

@@ -1,5 +1,3 @@
-// REQUIRES: host-supports-nvptx
-
 // RUN: mlir-opt %s \
 // RUN: | mlir-opt -test-lower-to-nvvm \
 // RUN: | mlir-cpu-runner \

mlir/test/Integration/GPU/CUDA/printf.mlir

@@ -1,5 +1,3 @@
-// REQUIRES: host-supports-nvptx
-
 // RUN: mlir-opt %s \
 // RUN: | mlir-opt -test-lower-to-nvvm \
 // RUN: | mlir-cpu-runner \

mlir/test/Integration/GPU/CUDA/shuffle.mlir

@@ -1,5 +1,3 @@
-// REQUIRES: host-supports-nvptx
-
 // RUN: mlir-opt %s \
 // RUN: | mlir-opt -test-lower-to-nvvm \
 // RUN: | mlir-cpu-runner \

mlir/test/Integration/GPU/CUDA/sm90/transform-dialect/tma_load_64x8_8x128_noswizzle-transform.mlir

@@ -1,5 +1,3 @@
-// REQUIRES: host-supports-nvptx
-
 // RUN: mlir-opt %s \
 // RUN:     -test-transform-dialect-interpreter \
 // RUN:     -test-transform-dialect-erase-schedule \

mlir/test/Integration/GPU/CUDA/two-modules.mlir

@@ -1,5 +1,3 @@
-// REQUIRES: host-supports-nvptx
-
 // RUN: mlir-opt %s \
 // RUN: | mlir-opt -test-lower-to-nvvm \
 // RUN: | mlir-cpu-runner \