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[x86] Add tan intrinsic part 4 (#90503)
This change is an implementation of #87367's investigation on supporting IEEE math operations as intrinsics. Which was discussed in this RFC: https://discourse.llvm.org/t/rfc-all-the-math-intrinsics/78294 Much of this change was following how G_FSIN and G_FCOS were used. Changes: - `llvm/docs/GlobalISel/GenericOpcode.rst` - Document the `G_FTAN` opcode - `llvm/docs/LangRef.rst` - Document the tan intrinsic - `llvm/include/llvm/Analysis/VecFuncs.def` - Associate the tan intrinsic as a vector function similar to the tanf libcall. - `llvm/include/llvm/CodeGen/BasicTTIImpl.h` - Map the tan intrinsic to `ISD::FTAN` - `llvm/include/llvm/CodeGen/ISDOpcodes.h` - Define ISD opcodes for `FTAN` and `STRICT_FTAN` - `llvm/include/llvm/IR/Intrinsics.td` - Create the tan intrinsic - `llvm/include/llvm/IR/RuntimeLibcalls.def` - Define tan libcall mappings - `llvm/include/llvm/Target/GenericOpcodes.td` - Define the `G_FTAN` Opcode - `llvm/include/llvm/Support/TargetOpcodes.def` - Create a `G_FTAN` Opcode handler - `llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td` - Map `G_FTAN` to `ftan` - `llvm/include/llvm/Target/TargetSelectionDAG.td` - Define `ftan`, `strict_ftan`, and `any_ftan` and map them to the ISD opcodes for `FTAN` and `STRICT_FTAN` - `llvm/lib/Analysis/VectorUtils.cpp` - Associate the tan intrinsic as a vector intrinsic - `llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp` Map the tan intrinsic to `G_FTAN` Opcode - `llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp` - Add `G_FTAN` to the list of floating point math operations also associate `G_FTAN` with the `TAN_F` runtime lib. - `llvm/lib/CodeGen/GlobalISel/Utils.cpp` - More floating point math operation common behaviors. - llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp - List the function expansion operations for `FTAN` and `STRICT_FTAN`. Also define both opcodes in `PromoteNode`. - `llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp` - More `FTAN` and `STRICT_FTAN` handling in the legalizer - `llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h` - Define `SoftenFloatRes_FTAN` and `ExpandFloatRes_FTAN`. - `llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp` - Define `FTAN` as a legal vector operation. - `llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp` - Define `FTAN` as a legal vector operation. - `llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp` - define tan as an intrinsic that doesn't return NaN. - `llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp` Map `LibFunc_tan`, `LibFunc_tanf`, and `LibFunc_tanl` to `ISD::FTAN`. Map `Intrinsic::tan` to `ISD::FTAN` and add selection dag handling for `Intrinsic::tan`. - `llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp` - Define `ftan` and `strict_ftan` names for the equivalent ISD opcodes. - `llvm/lib/CodeGen/TargetLoweringBase.cpp` -Define a Tan128 libcall and ISD::FTAN as a target lowering action. - `llvm/lib/Target/X86/X86ISelLowering.cpp` - Add x86_64 lowering for tan intrinsic resolves #70082
1 parent 3d44926 commit 1d87433

25 files changed

+700
-4
lines changed

‎llvm/include/llvm/Analysis/VecFuncs.def

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,7 @@ TLI_DEFINE_VECFUNC("llvm.sin.f32", "vsinf", FIXED(4), "_ZGV_LLVM_N4v")
4949
TLI_DEFINE_VECFUNC("cosf", "vcosf", FIXED(4), "_ZGV_LLVM_N4v")
5050
TLI_DEFINE_VECFUNC("llvm.cos.f32", "vcosf", FIXED(4), "_ZGV_LLVM_N4v")
5151
TLI_DEFINE_VECFUNC("tanf", "vtanf", FIXED(4), "_ZGV_LLVM_N4v")
52+
TLI_DEFINE_VECFUNC("llvm.tan.f32", "vtanf", FIXED(4), "_ZGV_LLVM_N4v")
5253
TLI_DEFINE_VECFUNC("asinf", "vasinf", FIXED(4), "_ZGV_LLVM_N4v")
5354
TLI_DEFINE_VECFUNC("acosf", "vacosf", FIXED(4), "_ZGV_LLVM_N4v")
5455
TLI_DEFINE_VECFUNC("atanf", "vatanf", FIXED(4), "_ZGV_LLVM_N4v")
@@ -142,6 +143,18 @@ TLI_DEFINE_VECFUNC("llvm.cos.f64", "_ZGVdN4v_cos", FIXED(4), "_ZGV_LLVM_N4v")
142143
TLI_DEFINE_VECFUNC("llvm.cos.f32", "_ZGVbN4v_cosf", FIXED(4), "_ZGV_LLVM_N4v")
143144
TLI_DEFINE_VECFUNC("llvm.cos.f32", "_ZGVdN8v_cosf", FIXED(8), "_ZGV_LLVM_N8v")
144145

146+
TLI_DEFINE_VECFUNC("tan", "_ZGVbN2v_tan", FIXED(2), "_ZGV_LLVM_N2v")
147+
TLI_DEFINE_VECFUNC("tan", "_ZGVdN4v_tan", FIXED(4), "_ZGV_LLVM_N4v")
148+
149+
TLI_DEFINE_VECFUNC("tanf", "_ZGVbN4v_tanf", FIXED(4), "_ZGV_LLVM_N4v")
150+
TLI_DEFINE_VECFUNC("tanf", "_ZGVdN8v_tanf", FIXED(8), "_ZGV_LLVM_N8v")
151+
152+
TLI_DEFINE_VECFUNC("llvm.tan.f64", "_ZGVbN2v_tan", FIXED(2), "_ZGV_LLVM_N2v")
153+
TLI_DEFINE_VECFUNC("llvm.tan.f64", "_ZGVdN4v_tan", FIXED(4), "_ZGV_LLVM_N4v")
154+
155+
TLI_DEFINE_VECFUNC("llvm.tan.f32", "_ZGVbN4v_tanf", FIXED(4), "_ZGV_LLVM_N4v")
156+
TLI_DEFINE_VECFUNC("llvm.tan.f32", "_ZGVdN8v_tanf", FIXED(8), "_ZGV_LLVM_N8v")
157+
145158
TLI_DEFINE_VECFUNC("pow", "_ZGVbN2vv_pow", FIXED(2), "_ZGV_LLVM_N2vv")
146159
TLI_DEFINE_VECFUNC("pow", "_ZGVdN4vv_pow", FIXED(4), "_ZGV_LLVM_N4vv")
147160

@@ -303,6 +316,22 @@ TLI_DEFINE_VECFUNC("llvm.cos.f32", "__svml_cosf4", FIXED(4), "_ZGV_LLVM_N4v")
303316
TLI_DEFINE_VECFUNC("llvm.cos.f32", "__svml_cosf8", FIXED(8), "_ZGV_LLVM_N8v")
304317
TLI_DEFINE_VECFUNC("llvm.cos.f32", "__svml_cosf16", FIXED(16), "_ZGV_LLVM_N16v")
305318

319+
TLI_DEFINE_VECFUNC("tan", "__svml_tan2", FIXED(2), "_ZGV_LLVM_N2v")
320+
TLI_DEFINE_VECFUNC("tan", "__svml_tan4", FIXED(4), "_ZGV_LLVM_N4v")
321+
TLI_DEFINE_VECFUNC("tan", "__svml_tan8", FIXED(8), "_ZGV_LLVM_N8v")
322+
323+
TLI_DEFINE_VECFUNC("tanf", "__svml_tanf4", FIXED(4), "_ZGV_LLVM_N4v")
324+
TLI_DEFINE_VECFUNC("tanf", "__svml_tanf8", FIXED(8), "_ZGV_LLVM_N8v")
325+
TLI_DEFINE_VECFUNC("tanf", "__svml_tanf16", FIXED(16), "_ZGV_LLVM_N16v")
326+
327+
TLI_DEFINE_VECFUNC("llvm.tan.f64", "__svml_tan2", FIXED(2), "_ZGV_LLVM_N2v")
328+
TLI_DEFINE_VECFUNC("llvm.tan.f64", "__svml_tan4", FIXED(4), "_ZGV_LLVM_N4v")
329+
TLI_DEFINE_VECFUNC("llvm.tan.f64", "__svml_tan8", FIXED(8), "_ZGV_LLVM_N8v")
330+
331+
TLI_DEFINE_VECFUNC("llvm.tan.f32", "__svml_tanf4", FIXED(4), "_ZGV_LLVM_N4v")
332+
TLI_DEFINE_VECFUNC("llvm.tan.f32", "__svml_tanf8", FIXED(8), "_ZGV_LLVM_N8v")
333+
TLI_DEFINE_VECFUNC("llvm.tan.f32", "__svml_tanf16", FIXED(16), "_ZGV_LLVM_N16v")
334+
306335
TLI_DEFINE_VECFUNC("pow", "__svml_pow2", FIXED(2), "_ZGV_LLVM_N2vv")
307336
TLI_DEFINE_VECFUNC("pow", "__svml_pow4", FIXED(4), "_ZGV_LLVM_N4vv")
308337
TLI_DEFINE_VECFUNC("pow", "__svml_pow8", FIXED(8), "_ZGV_LLVM_N8vv")
@@ -1237,6 +1266,13 @@ TLI_DEFINE_VECFUNC("tanf", "amd_vrs4_tanf", FIXED(4), NOMASK, "_ZGV_LLVM_N4v")
12371266
TLI_DEFINE_VECFUNC("tanf", "amd_vrs8_tanf", FIXED(8), NOMASK, "_ZGV_LLVM_N8v")
12381267
TLI_DEFINE_VECFUNC("tanf", "amd_vrs16_tanf", FIXED(16), NOMASK, "_ZGV_LLVM_N16v")
12391268

1269+
TLI_DEFINE_VECFUNC("llvm.tan.f32", "amd_vrs16_tanf", FIXED(16), NOMASK, "_ZGV_LLVM_N16v")
1270+
TLI_DEFINE_VECFUNC("llvm.tan.f32", "amd_vrs8_tanf", FIXED(8), NOMASK, "_ZGV_LLVM_N8v")
1271+
TLI_DEFINE_VECFUNC("llvm.tan.f32", "amd_vrs4_tanf", FIXED(4), NOMASK, "_ZGV_LLVM_N4v")
1272+
TLI_DEFINE_VECFUNC("llvm.tan.f64", "amd_vrd8_tan", FIXED(8), NOMASK, "_ZGV_LLVM_N8v")
1273+
TLI_DEFINE_VECFUNC("llvm.tan.f64", "amd_vrd4_tan", FIXED(4), NOMASK, "_ZGV_LLVM_N4v")
1274+
TLI_DEFINE_VECFUNC("llvm.tan.f64", "amd_vrd2_tan", FIXED(2), NOMASK, "_ZGV_LLVM_N2v")
1275+
12401276
TLI_DEFINE_VECFUNC("asin", "amd_vrd8_asin", FIXED(8), NOMASK, "_ZGV_LLVM_N8v")
12411277
TLI_DEFINE_VECFUNC("asinf", "amd_vrs4_asinf", FIXED(4), NOMASK, "_ZGV_LLVM_N4v")
12421278
TLI_DEFINE_VECFUNC("asinf", "amd_vrs8_asinf", FIXED(8), NOMASK, "_ZGV_LLVM_N8v")

‎llvm/include/llvm/CodeGen/BasicTTIImpl.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1977,6 +1977,9 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
19771977
case Intrinsic::cos:
19781978
ISD = ISD::FCOS;
19791979
break;
1980+
case Intrinsic::tan:
1981+
ISD = ISD::FTAN;
1982+
break;
19801983
case Intrinsic::exp:
19811984
ISD = ISD::FEXP;
19821985
break;

‎llvm/include/llvm/CodeGen/ISDOpcodes.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -415,6 +415,7 @@ enum NodeType {
415415
STRICT_FLDEXP,
416416
STRICT_FSIN,
417417
STRICT_FCOS,
418+
STRICT_FTAN,
418419
STRICT_FEXP,
419420
STRICT_FEXP2,
420421
STRICT_FLOG,
@@ -934,6 +935,7 @@ enum NodeType {
934935
FCBRT,
935936
FSIN,
936937
FCOS,
938+
FTAN,
937939
FPOW,
938940
FPOWI,
939941
/// FLDEXP - ldexp, inspired by libm (op0 * 2**op1).

‎llvm/include/llvm/IR/RuntimeLibcalls.def

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -197,6 +197,11 @@ HANDLE_LIBCALL(COS_F64, "cos")
197197
HANDLE_LIBCALL(COS_F80, "cosl")
198198
HANDLE_LIBCALL(COS_F128, "cosl")
199199
HANDLE_LIBCALL(COS_PPCF128, "cosl")
200+
HANDLE_LIBCALL(TAN_F32, "tanf")
201+
HANDLE_LIBCALL(TAN_F64, "tan")
202+
HANDLE_LIBCALL(TAN_F80, "tanl")
203+
HANDLE_LIBCALL(TAN_F128,"tanl")
204+
HANDLE_LIBCALL(TAN_PPCF128, "tanl")
200205
HANDLE_LIBCALL(SINCOS_F32, nullptr)
201206
HANDLE_LIBCALL(SINCOS_F64, nullptr)
202207
HANDLE_LIBCALL(SINCOS_F80, nullptr)

‎llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -148,6 +148,7 @@ def : GINodeEquiv<G_BUILD_VECTOR, build_vector>;
148148
def : GINodeEquiv<G_FCEIL, fceil>;
149149
def : GINodeEquiv<G_FCOS, fcos>;
150150
def : GINodeEquiv<G_FSIN, fsin>;
151+
def : GINodeEquiv<G_FTAN, ftan>;
151152
def : GINodeEquiv<G_FABS, fabs>;
152153
def : GINodeEquiv<G_FSQRT, fsqrt>;
153154
def : GINodeEquiv<G_FFLOOR, ffloor>;

‎llvm/include/llvm/Target/TargetSelectionDAG.td

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -509,6 +509,7 @@ def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
509509
def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
510510
def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
511511
def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
512+
def ftan : SDNode<"ISD::FTAN" , SDTFPUnaryOp>;
512513
def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;
513514
def fexp10 : SDNode<"ISD::FEXP10" , SDTFPUnaryOp>;
514515
def fpow : SDNode<"ISD::FPOW" , SDTFPBinOp>;
@@ -562,6 +563,8 @@ def strict_fsin : SDNode<"ISD::STRICT_FSIN",
562563
SDTFPUnaryOp, [SDNPHasChain]>;
563564
def strict_fcos : SDNode<"ISD::STRICT_FCOS",
564565
SDTFPUnaryOp, [SDNPHasChain]>;
566+
def strict_ftan : SDNode<"ISD::STRICT_FTAN",
567+
SDTFPUnaryOp, [SDNPHasChain]>;
565568
def strict_fexp2 : SDNode<"ISD::STRICT_FEXP2",
566569
SDTFPUnaryOp, [SDNPHasChain]>;
567570
def strict_fpow : SDNode<"ISD::STRICT_FPOW",
@@ -1517,6 +1520,9 @@ def any_fsin : PatFrags<(ops node:$src),
15171520
def any_fcos : PatFrags<(ops node:$src),
15181521
[(strict_fcos node:$src),
15191522
(fcos node:$src)]>;
1523+
def any_ftan : PatFrags<(ops node:$src),
1524+
[(strict_ftan node:$src),
1525+
(ftan node:$src)]>;
15201526
def any_fexp2 : PatFrags<(ops node:$src),
15211527
[(strict_fexp2 node:$src),
15221528
(fexp2 node:$src)]>;

‎llvm/lib/Analysis/VectorUtils.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,7 @@ bool llvm::isTriviallyVectorizable(Intrinsic::ID ID) {
6868
case Intrinsic::sqrt: // Begin floating-point.
6969
case Intrinsic::sin:
7070
case Intrinsic::cos:
71+
case Intrinsic::tan:
7172
case Intrinsic::exp:
7273
case Intrinsic::exp2:
7374
case Intrinsic::log:

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -449,6 +449,8 @@ static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
449449
RTLIBCASE(SIN_F);
450450
case TargetOpcode::G_FCOS:
451451
RTLIBCASE(COS_F);
452+
case TargetOpcode::G_FTAN:
453+
RTLIBCASE(TAN_F);
452454
case TargetOpcode::G_FLOG10:
453455
RTLIBCASE(LOG10_F);
454456
case TargetOpcode::G_FLOG:
@@ -1037,6 +1039,7 @@ LegalizerHelper::libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver) {
10371039
case TargetOpcode::G_FREM:
10381040
case TargetOpcode::G_FCOS:
10391041
case TargetOpcode::G_FSIN:
1042+
case TargetOpcode::G_FTAN:
10401043
case TargetOpcode::G_FLOG10:
10411044
case TargetOpcode::G_FLOG:
10421045
case TargetOpcode::G_FLOG2:
@@ -2893,6 +2896,7 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
28932896
case TargetOpcode::G_FFLOOR:
28942897
case TargetOpcode::G_FCOS:
28952898
case TargetOpcode::G_FSIN:
2899+
case TargetOpcode::G_FTAN:
28962900
case TargetOpcode::G_FLOG10:
28972901
case TargetOpcode::G_FLOG:
28982902
case TargetOpcode::G_FLOG2:
@@ -4659,6 +4663,7 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
46594663
case G_INTRINSIC_TRUNC:
46604664
case G_FCOS:
46614665
case G_FSIN:
4666+
case G_FTAN:
46624667
case G_FSQRT:
46634668
case G_BSWAP:
46644669
case G_BITREVERSE:

‎llvm/lib/CodeGen/GlobalISel/Utils.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -833,6 +833,7 @@ bool llvm::isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI,
833833
case TargetOpcode::G_FREM:
834834
case TargetOpcode::G_FSIN:
835835
case TargetOpcode::G_FCOS:
836+
case TargetOpcode::G_FTAN:
836837
case TargetOpcode::G_FMA:
837838
case TargetOpcode::G_FMAD:
838839
if (SNaN)
@@ -1713,6 +1714,7 @@ bool llvm::isPreISelGenericFloatingPointOpcode(unsigned Opc) {
17131714
case TargetOpcode::G_FREM:
17141715
case TargetOpcode::G_FRINT:
17151716
case TargetOpcode::G_FSIN:
1717+
case TargetOpcode::G_FTAN:
17161718
case TargetOpcode::G_FSQRT:
17171719
case TargetOpcode::G_FSUB:
17181720
case TargetOpcode::G_INTRINSIC_ROUND:

‎llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4514,6 +4514,11 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
45144514
RTLIB::COS_F80, RTLIB::COS_F128,
45154515
RTLIB::COS_PPCF128, Results);
45164516
break;
4517+
case ISD::FTAN:
4518+
case ISD::STRICT_FTAN:
4519+
ExpandFPLibCall(Node, RTLIB::TAN_F32, RTLIB::TAN_F64, RTLIB::TAN_F80,
4520+
RTLIB::TAN_F128, RTLIB::TAN_PPCF128, Results);
4521+
break;
45174522
case ISD::FSINCOS:
45184523
// Expand into sincos libcall.
45194524
ExpandSinCosLibCall(Node, Results);
@@ -5468,6 +5473,7 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
54685473
case ISD::FSQRT:
54695474
case ISD::FSIN:
54705475
case ISD::FCOS:
5476+
case ISD::FTAN:
54715477
case ISD::FLOG:
54725478
case ISD::FLOG2:
54735479
case ISD::FLOG10:
@@ -5492,6 +5498,7 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
54925498
case ISD::STRICT_FSQRT:
54935499
case ISD::STRICT_FSIN:
54945500
case ISD::STRICT_FCOS:
5501+
case ISD::STRICT_FTAN:
54955502
case ISD::STRICT_FLOG:
54965503
case ISD::STRICT_FLOG2:
54975504
case ISD::STRICT_FLOG10:

‎llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

Lines changed: 23 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -131,6 +131,8 @@ void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
131131
case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break;
132132
case ISD::STRICT_FSUB:
133133
case ISD::FSUB: R = SoftenFloatRes_FSUB(N); break;
134+
case ISD::STRICT_FTAN:
135+
case ISD::FTAN: R = SoftenFloatRes_FTAN(N); break;
134136
case ISD::STRICT_FTRUNC:
135137
case ISD::FTRUNC: R = SoftenFloatRes_FTRUNC(N); break;
136138
case ISD::LOAD: R = SoftenFloatRes_LOAD(N); break;
@@ -774,6 +776,12 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FSUB(SDNode *N) {
774776
RTLIB::SUB_PPCF128));
775777
}
776778

779+
SDValue DAGTypeLegalizer::SoftenFloatRes_FTAN(SDNode *N) {
780+
return SoftenFloatRes_Unary(
781+
N, GetFPLibCall(N->getValueType(0), RTLIB::TAN_F32, RTLIB::TAN_F64,
782+
RTLIB::TAN_F80, RTLIB::TAN_F128, RTLIB::TAN_PPCF128));
783+
}
784+
777785
SDValue DAGTypeLegalizer::SoftenFloatRes_FTRUNC(SDNode *N) {
778786
return SoftenFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
779787
RTLIB::TRUNC_F32,
@@ -1330,7 +1338,7 @@ void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) {
13301338
#endif
13311339
report_fatal_error("Do not know how to expand the result of this "
13321340
"operator!");
1333-
1341+
// clang-format off
13341342
case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
13351343
case ISD::SELECT: SplitRes_Select(N, Lo, Hi); break;
13361344
case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
@@ -1399,6 +1407,8 @@ void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) {
13991407
case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break;
14001408
case ISD::STRICT_FSUB:
14011409
case ISD::FSUB: ExpandFloatRes_FSUB(N, Lo, Hi); break;
1410+
case ISD::STRICT_FTAN:
1411+
case ISD::FTAN: ExpandFloatRes_FTAN(N, Lo, Hi); break;
14021412
case ISD::STRICT_FTRUNC:
14031413
case ISD::FTRUNC: ExpandFloatRes_FTRUNC(N, Lo, Hi); break;
14041414
case ISD::LOAD: ExpandFloatRes_LOAD(N, Lo, Hi); break;
@@ -1408,6 +1418,7 @@ void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) {
14081418
case ISD::UINT_TO_FP: ExpandFloatRes_XINT_TO_FP(N, Lo, Hi); break;
14091419
case ISD::STRICT_FREM:
14101420
case ISD::FREM: ExpandFloatRes_FREM(N, Lo, Hi); break;
1421+
// clang-format on
14111422
}
14121423

14131424
// If Lo/Hi is null, the sub-method took care of registering results etc.
@@ -1768,6 +1779,15 @@ void DAGTypeLegalizer::ExpandFloatRes_FSUB(SDNode *N, SDValue &Lo,
17681779
RTLIB::SUB_PPCF128), Lo, Hi);
17691780
}
17701781

1782+
void DAGTypeLegalizer::ExpandFloatRes_FTAN(SDNode *N, SDValue &Lo,
1783+
SDValue &Hi) {
1784+
ExpandFloatRes_Unary(N,
1785+
GetFPLibCall(N->getValueType(0), RTLIB::TAN_F32,
1786+
RTLIB::TAN_F64, RTLIB::TAN_F80,
1787+
RTLIB::TAN_F128, RTLIB::TAN_PPCF128),
1788+
Lo, Hi);
1789+
}
1790+
17711791
void DAGTypeLegalizer::ExpandFloatRes_FTRUNC(SDNode *N,
17721792
SDValue &Lo, SDValue &Hi) {
17731793
ExpandFloatRes_Unary(N, GetFPLibCall(N->getValueType(0),
@@ -2479,6 +2499,7 @@ void DAGTypeLegalizer::PromoteFloatResult(SDNode *N, unsigned ResNo) {
24792499
case ISD::FSIN:
24802500
case ISD::FSQRT:
24812501
case ISD::FTRUNC:
2502+
case ISD::FTAN:
24822503
case ISD::FCANONICALIZE: R = PromoteFloatRes_UnaryOp(N); break;
24832504

24842505
// Binary FP Operations
@@ -2914,6 +2935,7 @@ void DAGTypeLegalizer::SoftPromoteHalfResult(SDNode *N, unsigned ResNo) {
29142935
case ISD::FSIN:
29152936
case ISD::FSQRT:
29162937
case ISD::FTRUNC:
2938+
case ISD::FTAN:
29172939
case ISD::FCANONICALIZE: R = SoftPromoteHalfRes_UnaryOp(N); break;
29182940

29192941
// Binary FP Operations

‎llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -586,6 +586,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
586586
SDValue SoftenFloatRes_FSIN(SDNode *N);
587587
SDValue SoftenFloatRes_FSQRT(SDNode *N);
588588
SDValue SoftenFloatRes_FSUB(SDNode *N);
589+
SDValue SoftenFloatRes_FTAN(SDNode *N);
589590
SDValue SoftenFloatRes_FTRUNC(SDNode *N);
590591
SDValue SoftenFloatRes_LOAD(SDNode *N);
591592
SDValue SoftenFloatRes_ATOMIC_LOAD(SDNode *N);
@@ -635,6 +636,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
635636
SDValue &Lo, SDValue &Hi);
636637
void ExpandFloatRes_Binary(SDNode *N, RTLIB::Libcall LC,
637638
SDValue &Lo, SDValue &Hi);
639+
// clang-format off
638640
void ExpandFloatRes_FABS (SDNode *N, SDValue &Lo, SDValue &Hi);
639641
void ExpandFloatRes_FMINNUM (SDNode *N, SDValue &Lo, SDValue &Hi);
640642
void ExpandFloatRes_FMAXNUM (SDNode *N, SDValue &Lo, SDValue &Hi);
@@ -667,9 +669,11 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
667669
void ExpandFloatRes_FSIN (SDNode *N, SDValue &Lo, SDValue &Hi);
668670
void ExpandFloatRes_FSQRT (SDNode *N, SDValue &Lo, SDValue &Hi);
669671
void ExpandFloatRes_FSUB (SDNode *N, SDValue &Lo, SDValue &Hi);
672+
void ExpandFloatRes_FTAN (SDNode *N, SDValue &Lo, SDValue &Hi);
670673
void ExpandFloatRes_FTRUNC (SDNode *N, SDValue &Lo, SDValue &Hi);
671674
void ExpandFloatRes_LOAD (SDNode *N, SDValue &Lo, SDValue &Hi);
672675
void ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo, SDValue &Hi);
676+
// clang-format on
673677

674678
// Float Operand Expansion.
675679
bool ExpandFloatOperand(SDNode *N, unsigned OpNo);

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -397,6 +397,7 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
397397
case ISD::FSQRT:
398398
case ISD::FSIN:
399399
case ISD::FCOS:
400+
case ISD::FTAN:
400401
case ISD::FLDEXP:
401402
case ISD::FPOWI:
402403
case ISD::FPOW:

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -108,6 +108,7 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
108108
case ISD::FROUNDEVEN:
109109
case ISD::FSIN:
110110
case ISD::FSQRT:
111+
case ISD::FTAN:
111112
case ISD::FTRUNC:
112113
case ISD::SIGN_EXTEND:
113114
case ISD::SINT_TO_FP:
@@ -1140,6 +1141,7 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
11401141
case ISD::VP_FROUNDEVEN:
11411142
case ISD::FSIN:
11421143
case ISD::FSQRT: case ISD::VP_SQRT:
1144+
case ISD::FTAN:
11431145
case ISD::FTRUNC:
11441146
case ISD::VP_FROUNDTOZERO:
11451147
case ISD::SINT_TO_FP:
@@ -4400,6 +4402,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
44004402
case ISD::FROUNDEVEN:
44014403
case ISD::FSIN:
44024404
case ISD::FSQRT:
4405+
case ISD::FTAN:
44034406
case ISD::FTRUNC:
44044407
if (unrollExpandedOp())
44054408
break;

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5375,6 +5375,7 @@ bool SelectionDAG::isKnownNeverNaN(SDValue Op, bool SNaN, unsigned Depth) const
53755375
case ISD::FREM:
53765376
case ISD::FSIN:
53775377
case ISD::FCOS:
5378+
case ISD::FTAN:
53785379
case ISD::FMA:
53795380
case ISD::FMAD: {
53805381
if (SNaN)

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6742,6 +6742,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
67426742
case Intrinsic::fabs:
67436743
case Intrinsic::sin:
67446744
case Intrinsic::cos:
6745+
case Intrinsic::tan:
67456746
case Intrinsic::exp10:
67466747
case Intrinsic::floor:
67476748
case Intrinsic::ceil:
@@ -6759,6 +6760,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
67596760
case Intrinsic::fabs: Opcode = ISD::FABS; break;
67606761
case Intrinsic::sin: Opcode = ISD::FSIN; break;
67616762
case Intrinsic::cos: Opcode = ISD::FCOS; break;
6763+
case Intrinsic::tan: Opcode = ISD::FTAN; break;
67626764
case Intrinsic::exp10: Opcode = ISD::FEXP10; break;
67636765
case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
67646766
case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
@@ -9160,6 +9162,12 @@ void SelectionDAGBuilder::visitCall(const CallInst &I) {
91609162
if (visitUnaryFloatCall(I, ISD::FCOS))
91619163
return;
91629164
break;
9165+
case LibFunc_tan:
9166+
case LibFunc_tanf:
9167+
case LibFunc_tanl:
9168+
if (visitUnaryFloatCall(I, ISD::FTAN))
9169+
return;
9170+
break;
91639171
case LibFunc_sqrt:
91649172
case LibFunc_sqrtf:
91659173
case LibFunc_sqrtl:

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