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[AMDGPU][Attributor] Rework calculation of waves per eu
resolve review comments rebase and resolve review comments
1 parent 35fda65 commit 1e140dd

33 files changed

+336
-283
lines changed

llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp

Lines changed: 85 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -1117,47 +1117,25 @@ struct AAAMDWavesPerEU : public AAAMDSizeRangeAttribute {
11171117
Function *F = getAssociatedFunction();
11181118
auto &InfoCache = static_cast<AMDGPUInformationCache &>(A.getInfoCache());
11191119

1120-
auto TakeRange = [&](std::pair<unsigned, unsigned> R) {
1121-
auto [Min, Max] = R;
1122-
ConstantRange Range(APInt(32, Min), APInt(32, Max + 1));
1123-
IntegerRangeState RangeState(Range);
1124-
clampStateAndIndicateChange(this->getState(), RangeState);
1125-
indicateOptimisticFixpoint();
1126-
};
1127-
1128-
std::pair<unsigned, unsigned> MaxWavesPerEURange{
1129-
1U, InfoCache.getMaxWavesPerEU(*F)};
1130-
11311120
// If the attribute exists, we will honor it if it is not the default.
11321121
if (auto Attr = InfoCache.getWavesPerEUAttr(*F)) {
1122+
std::pair<unsigned, unsigned> MaxWavesPerEURange{
1123+
1U, InfoCache.getMaxWavesPerEU(*F)};
11331124
if (*Attr != MaxWavesPerEURange) {
1134-
TakeRange(*Attr);
1125+
auto [Min, Max] = *Attr;
1126+
ConstantRange Range(APInt(32, Min), APInt(32, Max + 1));
1127+
IntegerRangeState RangeState(Range);
1128+
this->getState() = RangeState;
1129+
indicateOptimisticFixpoint();
11351130
return;
11361131
}
11371132
}
11381133

1139-
// Unlike AAAMDFlatWorkGroupSize, it's getting trickier here. Since the
1140-
// calculation of waves per EU involves flat work group size, we can't
1141-
// simply use an assumed flat work group size as a start point, because the
1142-
// update of flat work group size is in an inverse direction of waves per
1143-
// EU. However, we can still do something if it is an entry function. Since
1144-
// an entry function is a terminal node, and flat work group size either
1145-
// from attribute or default will be used anyway, we can take that value and
1146-
// calculate the waves per EU based on it. This result can't be updated by
1147-
// no means, but that could still allow us to propagate it.
1148-
if (AMDGPU::isEntryFunctionCC(F->getCallingConv())) {
1149-
std::pair<unsigned, unsigned> FlatWorkGroupSize;
1150-
if (auto Attr = InfoCache.getFlatWorkGroupSizeAttr(*F))
1151-
FlatWorkGroupSize = *Attr;
1152-
else
1153-
FlatWorkGroupSize = InfoCache.getDefaultFlatWorkGroupSize(*F);
1154-
TakeRange(InfoCache.getEffectiveWavesPerEU(*F, MaxWavesPerEURange,
1155-
FlatWorkGroupSize));
1156-
}
1134+
if (AMDGPU::isEntryFunctionCC(F->getCallingConv()))
1135+
indicatePessimisticFixpoint();
11571136
}
11581137

11591138
ChangeStatus updateImpl(Attributor &A) override {
1160-
auto &InfoCache = static_cast<AMDGPUInformationCache &>(A.getInfoCache());
11611139
ChangeStatus Change = ChangeStatus::UNCHANGED;
11621140

11631141
auto CheckCallSite = [&](AbstractCallSite CS) {
@@ -1166,24 +1144,21 @@ struct AAAMDWavesPerEU : public AAAMDSizeRangeAttribute {
11661144
LLVM_DEBUG(dbgs() << '[' << getName() << "] Call " << Caller->getName()
11671145
<< "->" << Func->getName() << '\n');
11681146

1169-
const auto *CallerInfo = A.getAAFor<AAAMDWavesPerEU>(
1147+
const auto *CallerAA = A.getAAFor<AAAMDWavesPerEU>(
11701148
*this, IRPosition::function(*Caller), DepClassTy::REQUIRED);
1171-
const auto *AssumedGroupSize = A.getAAFor<AAAMDFlatWorkGroupSize>(
1172-
*this, IRPosition::function(*Func), DepClassTy::REQUIRED);
1173-
if (!CallerInfo || !AssumedGroupSize || !CallerInfo->isValidState() ||
1174-
!AssumedGroupSize->isValidState())
1149+
if (!CallerAA || !CallerAA->isValidState())
11751150
return false;
11761151

1177-
unsigned Min, Max;
1178-
std::tie(Min, Max) = InfoCache.getEffectiveWavesPerEU(
1179-
*Caller,
1180-
{CallerInfo->getAssumed().getLower().getZExtValue(),
1181-
CallerInfo->getAssumed().getUpper().getZExtValue() - 1},
1182-
{AssumedGroupSize->getAssumed().getLower().getZExtValue(),
1183-
AssumedGroupSize->getAssumed().getUpper().getZExtValue() - 1});
1184-
ConstantRange CallerRange(APInt(32, Min), APInt(32, Max + 1));
1185-
IntegerRangeState CallerRangeState(CallerRange);
1186-
Change |= clampStateAndIndicateChange(this->getState(), CallerRangeState);
1152+
ConstantRange Assumed = this->getAssumed();
1153+
unsigned Min = std::max(Assumed.getLower().getZExtValue(),
1154+
CallerAA->getAssumed().getLower().getZExtValue());
1155+
unsigned Max = std::max(Assumed.getUpper().getZExtValue(),
1156+
CallerAA->getAssumed().getUpper().getZExtValue());
1157+
ConstantRange Range(APInt(32, Min), APInt(32, Max));
1158+
IntegerRangeState RangeState(Range);
1159+
this->getState() = RangeState;
1160+
Change |= this->getState() == Assumed ? ChangeStatus::UNCHANGED
1161+
: ChangeStatus::CHANGED;
11871162

11881163
return true;
11891164
};
@@ -1342,6 +1317,60 @@ static void addPreloadKernArgHint(Function &F, TargetMachine &TM) {
13421317
}
13431318
}
13441319

1320+
/// The final check and update of the attribute 'amdgpu-waves-per-eu' based on
1321+
/// the determined 'amdgpu-flat-work-group-size' attribute. We can't do this
1322+
/// during attributor run because the two attributes grow in opposite direction,
1323+
/// we should not use any intermediate value to calculate waves per eu until we
1324+
/// have a determined flat workgroup size.
1325+
static void updateWavesPerEU(Module &M, TargetMachine &TM) {
1326+
for (Function &F : M) {
1327+
if (F.isDeclaration())
1328+
continue;
1329+
1330+
const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F);
1331+
1332+
std::optional<std::pair<unsigned, std::optional<unsigned>>>
1333+
FlatWgrpSizeAttr =
1334+
AMDGPU::getIntegerPairAttribute(F, "amdgpu-flat-work-group-size");
1335+
1336+
unsigned MinWavesPerEU = ST.getMinWavesPerEU();
1337+
unsigned MaxWavesPerEU = ST.getMaxWavesPerEU();
1338+
1339+
unsigned MinFlatWgrpSize = ST.getMinFlatWorkGroupSize();
1340+
unsigned MaxFlatWgrpSize = ST.getMaxFlatWorkGroupSize();
1341+
if (FlatWgrpSizeAttr.has_value()) {
1342+
MinFlatWgrpSize = FlatWgrpSizeAttr->first;
1343+
MaxFlatWgrpSize = *(FlatWgrpSizeAttr->second);
1344+
}
1345+
1346+
// Start with the max range.
1347+
unsigned Min = MinWavesPerEU;
1348+
unsigned Max = MinWavesPerEU;
1349+
1350+
// Compute the range from flat workgroup size. `getWavesPerEU` will also
1351+
// account for the 'amdgpu-waves-er-eu' attribute.
1352+
auto [MinFromFlatWgrpSize, MaxFromFlatWgrpSize] =
1353+
ST.getWavesPerEU(F, {MinFlatWgrpSize, MaxFlatWgrpSize});
1354+
1355+
// For the lower bound, we have to "tighten" it.
1356+
Min = std::max(Min, MinFromFlatWgrpSize);
1357+
// For the upper bound, we have to "extend" it.
1358+
Max = std::max(Max, MaxFromFlatWgrpSize);
1359+
1360+
// Clamp the range to the max range.
1361+
Min = std::max(Min, MinWavesPerEU);
1362+
Max = std::min(Max, MaxWavesPerEU);
1363+
1364+
// Update the attribute if it is not the max.
1365+
if (Min != MinWavesPerEU || Max != MaxWavesPerEU) {
1366+
SmallString<10> Buffer;
1367+
raw_svector_ostream OS(Buffer);
1368+
OS << Min << ',' << Max;
1369+
F.addFnAttr("amdgpu-waves-per-eu", OS.str());
1370+
}
1371+
}
1372+
}
1373+
13451374
static bool runImpl(Module &M, AnalysisGetter &AG, TargetMachine &TM,
13461375
AMDGPUAttributorOptions Options,
13471376
ThinOrFullLTOPhase LTOPhase) {
@@ -1417,8 +1446,16 @@ static bool runImpl(Module &M, AnalysisGetter &AG, TargetMachine &TM,
14171446
}
14181447
}
14191448

1420-
ChangeStatus Change = A.run();
1421-
return Change == ChangeStatus::CHANGED;
1449+
bool Changed = A.run() == ChangeStatus::CHANGED;
1450+
1451+
// We only update the waves-per-eu attribute at the final stage to avoid
1452+
// setting it with intermediate values.
1453+
if (Changed && (LTOPhase == ThinOrFullLTOPhase::None ||
1454+
LTOPhase == ThinOrFullLTOPhase::FullLTOPostLink ||
1455+
LTOPhase == ThinOrFullLTOPhase::ThinLTOPostLink))
1456+
updateWavesPerEU(M, TM);
1457+
1458+
return Changed;
14221459
}
14231460

14241461
class AMDGPUAttributorLegacy : public ModulePass {

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -216,6 +216,15 @@ AMDGPUSubtarget::getWavesPerEU(const Function &F) const {
216216
return getWavesPerEU(FlatWorkGroupSizes, LDSBytes, F);
217217
}
218218

219+
std::pair<unsigned, unsigned> AMDGPUSubtarget::getWavesPerEU(
220+
const Function &F, std::pair<unsigned, unsigned> FlatWorkGroupSizes) const {
221+
// Minimum number of bytes allocated in the LDS.
222+
unsigned LDSBytes = AMDGPU::getIntegerPairAttribute(F, "amdgpu-lds-size",
223+
{0, UINT32_MAX}, true)
224+
.first;
225+
return getWavesPerEU(FlatWorkGroupSizes, LDSBytes, F);
226+
}
227+
219228
std::pair<unsigned, unsigned>
220229
AMDGPUSubtarget::getWavesPerEU(std::pair<unsigned, unsigned> FlatWorkGroupSizes,
221230
unsigned LDSBytes, const Function &F) const {

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -108,6 +108,13 @@ class AMDGPUSubtarget {
108108
/// size, register usage, and/or lds usage.
109109
std::pair<unsigned, unsigned> getWavesPerEU(const Function &F) const;
110110

111+
/// Overload which uses the specified values for the flat work group sizes,
112+
/// rather than querying the function itself. \p FlatWorkGroupSizes Should
113+
/// correspond to the function's value for getFlatWorkGroupSizes.
114+
std::pair<unsigned, unsigned>
115+
getWavesPerEU(const Function &F,
116+
std::pair<unsigned, unsigned> FlatWorkGroupSizes) const;
117+
111118
/// Overload which uses the specified values for the flat workgroup sizes and
112119
/// LDS space rather than querying the function itself. \p FlatWorkGroupSizes
113120
/// should correspond to the function's value for getFlatWorkGroupSizes and \p

llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -169,6 +169,6 @@ attributes #1 = { nounwind }
169169

170170
;.
171171
; HSA: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
172-
; HSA: attributes #[[ATTR1]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
173-
; HSA: attributes #[[ATTR2]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
172+
; HSA: attributes #[[ATTR1]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
173+
; HSA: attributes #[[ATTR2]] = { nounwind "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
174174
;.

llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-agpr.ll

Lines changed: 14 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -105,7 +105,7 @@ declare void @unknown()
105105

106106
define amdgpu_kernel void @kernel_calls_extern() {
107107
; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_extern(
108-
; CHECK-SAME: ) #[[ATTR2:[0-9]+]] {
108+
; CHECK-SAME: ) #[[ATTR3:[0-9]+]] {
109109
; CHECK-NEXT: call void @unknown()
110110
; CHECK-NEXT: ret void
111111
;
@@ -115,8 +115,8 @@ define amdgpu_kernel void @kernel_calls_extern() {
115115

116116
define amdgpu_kernel void @kernel_calls_extern_marked_callsite() {
117117
; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_extern_marked_callsite(
118-
; CHECK-SAME: ) #[[ATTR2]] {
119-
; CHECK-NEXT: call void @unknown() #[[ATTR6:[0-9]+]]
118+
; CHECK-SAME: ) #[[ATTR3]] {
119+
; CHECK-NEXT: call void @unknown() #[[ATTR7:[0-9]+]]
120120
; CHECK-NEXT: ret void
121121
;
122122
call void @unknown() #0
@@ -125,7 +125,7 @@ define amdgpu_kernel void @kernel_calls_extern_marked_callsite() {
125125

126126
define amdgpu_kernel void @kernel_calls_indirect(ptr %indirect) {
127127
; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_indirect(
128-
; CHECK-SAME: ptr [[INDIRECT:%.*]]) #[[ATTR2]] {
128+
; CHECK-SAME: ptr [[INDIRECT:%.*]]) #[[ATTR3]] {
129129
; CHECK-NEXT: call void [[INDIRECT]]()
130130
; CHECK-NEXT: ret void
131131
;
@@ -135,8 +135,8 @@ define amdgpu_kernel void @kernel_calls_indirect(ptr %indirect) {
135135

136136
define amdgpu_kernel void @kernel_calls_indirect_marked_callsite(ptr %indirect) {
137137
; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_indirect_marked_callsite(
138-
; CHECK-SAME: ptr [[INDIRECT:%.*]]) #[[ATTR2]] {
139-
; CHECK-NEXT: call void [[INDIRECT]]() #[[ATTR6]]
138+
; CHECK-SAME: ptr [[INDIRECT:%.*]]) #[[ATTR3]] {
139+
; CHECK-NEXT: call void [[INDIRECT]]() #[[ATTR7]]
140140
; CHECK-NEXT: ret void
141141
;
142142
call void %indirect() #0
@@ -254,11 +254,12 @@ define amdgpu_kernel void @indirect_calls_none_agpr(i1 %cond) {
254254

255255
attributes #0 = { "amdgpu-agpr-alloc"="0" }
256256
;.
257-
; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
258-
; CHECK: attributes #[[ATTR1]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
259-
; CHECK: attributes #[[ATTR2]] = { "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
260-
; CHECK: attributes #[[ATTR3:[0-9]+]] = { convergent nocallback nofree nosync nounwind willreturn memory(none) "target-cpu"="gfx90a" }
261-
; CHECK: attributes #[[ATTR4:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) "target-cpu"="gfx90a" }
262-
; CHECK: attributes #[[ATTR5:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) "target-cpu"="gfx90a" }
263-
; CHECK: attributes #[[ATTR6]] = { "amdgpu-agpr-alloc"="0" }
257+
; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,8" "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
258+
; CHECK: attributes #[[ATTR1]] = { "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-flat-scratch-init" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,8" "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
259+
; CHECK: attributes #[[ATTR2:[0-9]+]] = { "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
260+
; CHECK: attributes #[[ATTR3]] = { "amdgpu-waves-per-eu"="4,8" "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
261+
; CHECK: attributes #[[ATTR4:[0-9]+]] = { convergent nocallback nofree nosync nounwind willreturn memory(none) "target-cpu"="gfx90a" }
262+
; CHECK: attributes #[[ATTR5:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) "target-cpu"="gfx90a" }
263+
; CHECK: attributes #[[ATTR6:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) "target-cpu"="gfx90a" }
264+
; CHECK: attributes #[[ATTR7]] = { "amdgpu-agpr-alloc"="0" }
264265
;.

llvm/test/CodeGen/AMDGPU/annotate-existing-abi-attributes.ll

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -117,14 +117,14 @@ define void @call_no_dispatch_id() {
117117
ret void
118118
}
119119
;.
120-
; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-workitem-id-x" "uniform-work-group-size"="false" }
121-
; CHECK: attributes #[[ATTR1]] = { "amdgpu-no-workitem-id-y" "uniform-work-group-size"="false" }
122-
; CHECK: attributes #[[ATTR2]] = { "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
123-
; CHECK: attributes #[[ATTR3]] = { "amdgpu-no-workgroup-id-x" "uniform-work-group-size"="false" }
124-
; CHECK: attributes #[[ATTR4]] = { "amdgpu-no-workgroup-id-y" "uniform-work-group-size"="false" }
125-
; CHECK: attributes #[[ATTR5]] = { "amdgpu-no-workgroup-id-z" "uniform-work-group-size"="false" }
126-
; CHECK: attributes #[[ATTR6]] = { "amdgpu-no-dispatch-ptr" "uniform-work-group-size"="false" }
127-
; CHECK: attributes #[[ATTR7]] = { "amdgpu-no-queue-ptr" "uniform-work-group-size"="false" }
128-
; CHECK: attributes #[[ATTR8]] = { "amdgpu-no-implicitarg-ptr" "uniform-work-group-size"="false" }
129-
; CHECK: attributes #[[ATTR9]] = { "amdgpu-no-dispatch-id" "uniform-work-group-size"="false" }
120+
; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-workitem-id-x" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
121+
; CHECK: attributes #[[ATTR1]] = { "amdgpu-no-workitem-id-y" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
122+
; CHECK: attributes #[[ATTR2]] = { "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
123+
; CHECK: attributes #[[ATTR3]] = { "amdgpu-no-workgroup-id-x" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
124+
; CHECK: attributes #[[ATTR4]] = { "amdgpu-no-workgroup-id-y" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
125+
; CHECK: attributes #[[ATTR5]] = { "amdgpu-no-workgroup-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
126+
; CHECK: attributes #[[ATTR6]] = { "amdgpu-no-dispatch-ptr" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
127+
; CHECK: attributes #[[ATTR7]] = { "amdgpu-no-queue-ptr" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
128+
; CHECK: attributes #[[ATTR8]] = { "amdgpu-no-implicitarg-ptr" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
129+
; CHECK: attributes #[[ATTR9]] = { "amdgpu-no-dispatch-id" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
130130
;.

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