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[InitUndef] Don't use largest super class (#107885)
The InitUndef pass currently uses the getLargestSuperClass() hook (which is only used by that pass) to chose the register to initialize. This was done to reduce the number of undef init pseudos needed, e.g. so that the vrnov0 regclass would use the same pseudo as v0. After #106744 we use a single generic pseudo, so this is no longer necessary.
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5 files changed

+33
-70
lines changed

5 files changed

+33
-70
lines changed

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1204,15 +1204,6 @@ class TargetRegisterInfo : public MCRegisterInfo {
12041204
return false;
12051205
}
12061206

1207-
/// Returns the Largest Super Class that is being initialized. There
1208-
/// should be a Pseudo Instruction implemented for the super class
1209-
/// that is being returned to ensure that Init Undef can apply the
1210-
/// initialization correctly.
1211-
virtual const TargetRegisterClass *
1212-
getLargestSuperClass(const TargetRegisterClass *RC) const {
1213-
llvm_unreachable("Unexpected target register class.");
1214-
}
1215-
12161207
/// Returns if the architecture being targeted has the required Pseudo
12171208
/// Instructions for initializing the register. By default this returns false,
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/// but where it is overriden for an architecture, the behaviour will be

llvm/lib/CodeGen/InitUndef.cpp

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -152,8 +152,7 @@ bool InitUndef::handleSubReg(MachineFunction &MF, MachineInstr &MI,
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if (Info.UsedLanes == Info.DefinedLanes)
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continue;
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155-
const TargetRegisterClass *TargetRegClass =
156-
TRI->getLargestSuperClass(MRI->getRegClass(Reg));
155+
const TargetRegisterClass *TargetRegClass = MRI->getRegClass(Reg);
157156

158157
LaneBitmask NeedDef = Info.UsedLanes & ~Info.DefinedLanes;
159158

@@ -172,8 +171,8 @@ bool InitUndef::handleSubReg(MachineFunction &MF, MachineInstr &MI,
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Register LatestReg = Reg;
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for (auto ind : SubRegIndexNeedInsert) {
174173
Changed = true;
175-
const TargetRegisterClass *SubRegClass = TRI->getLargestSuperClass(
176-
TRI->getSubRegisterClass(TargetRegClass, ind));
174+
const TargetRegisterClass *SubRegClass =
175+
TRI->getSubRegisterClass(TargetRegClass, ind);
177176
Register TmpInitSubReg = MRI->createVirtualRegister(SubRegClass);
178177
LLVM_DEBUG(dbgs() << "Register Class ID" << SubRegClass->getID() << "\n");
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BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(),
@@ -199,8 +198,7 @@ bool InitUndef::fixupIllOperand(MachineInstr *MI, MachineOperand &MO) {
199198
dbgs() << "Emitting PseudoInitUndef Instruction for implicit register "
200199
<< printReg(MO.getReg()) << '\n');
201200

202-
const TargetRegisterClass *TargetRegClass =
203-
TRI->getLargestSuperClass(MRI->getRegClass(MO.getReg()));
201+
const TargetRegisterClass *TargetRegClass = MRI->getRegClass(MO.getReg());
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LLVM_DEBUG(dbgs() << "Register Class ID" << TargetRegClass->getID() << "\n");
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Register NewReg = MRI->createVirtualRegister(TargetRegClass);
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BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),

llvm/lib/Target/ARM/ARMBaseRegisterInfo.h

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -241,19 +241,6 @@ class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
241241

242242
int getSEHRegNum(unsigned i) const { return getEncodingValue(i); }
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244-
const TargetRegisterClass *
245-
getLargestSuperClass(const TargetRegisterClass *RC) const override {
246-
if (ARM::MQPRRegClass.hasSubClassEq(RC))
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return &ARM::MQPRRegClass;
248-
if (ARM::SPRRegClass.hasSubClassEq(RC))
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return &ARM::SPRRegClass;
250-
if (ARM::DPR_VFP2RegClass.hasSubClassEq(RC))
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return &ARM::DPR_VFP2RegClass;
252-
if (ARM::GPRRegClass.hasSubClassEq(RC))
253-
return &ARM::GPRRegClass;
254-
return RC;
255-
}
256-
257244
bool doesRegClassHavePseudoInitUndef(
258245
const TargetRegisterClass *RC) const override {
259246
(void)RC;

llvm/lib/Target/RISCV/RISCVRegisterInfo.h

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -130,19 +130,6 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
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const MachineFunction &MF, const VirtRegMap *VRM,
131131
const LiveRegMatrix *Matrix) const override;
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133-
const TargetRegisterClass *
134-
getLargestSuperClass(const TargetRegisterClass *RC) const override {
135-
if (RISCV::VRM8RegClass.hasSubClassEq(RC))
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return &RISCV::VRM8RegClass;
137-
if (RISCV::VRM4RegClass.hasSubClassEq(RC))
138-
return &RISCV::VRM4RegClass;
139-
if (RISCV::VRM2RegClass.hasSubClassEq(RC))
140-
return &RISCV::VRM2RegClass;
141-
if (RISCV::VRRegClass.hasSubClassEq(RC))
142-
return &RISCV::VRRegClass;
143-
return RC;
144-
}
145-
146133
bool doesRegClassHavePseudoInitUndef(
147134
const TargetRegisterClass *RC) const override {
148135
return isVRRegClass(RC);

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