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[X86][mem-fold] Remove the logic for FoldGenData, NFCI
1 parent 7c78cb4 commit 1e75ce4

9 files changed

+64
-115
lines changed

‎llvm/lib/Target/X86/X86InstrAVX512.td

Lines changed: 4 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -3533,21 +3533,19 @@ multiclass avx512_store<bits<8> opc, string OpcodeStr, string BaseName,
35333533
def rr_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
35343534
OpcodeStr # "\t{$src, $dst|$dst, $src}",
35353535
[], _.ExeDomain>, EVEX,
3536-
FoldGenData<BaseName#_.ZSuffix#rr>, Sched<[Sched.RR]>,
3536+
Sched<[Sched.RR]>,
35373537
EVEX2VEXOverride<EVEX2VEXOvrd#"rr_REV">;
35383538
def rrk_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
35393539
(ins _.KRCWM:$mask, _.RC:$src),
35403540
OpcodeStr # "\t{$src, ${dst} {${mask}}|"#
35413541
"${dst} {${mask}}, $src}",
35423542
[], _.ExeDomain>, EVEX, EVEX_K,
3543-
FoldGenData<BaseName#_.ZSuffix#rrk>,
35443543
Sched<[Sched.RR]>;
35453544
def rrkz_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
35463545
(ins _.KRCWM:$mask, _.RC:$src),
35473546
OpcodeStr # "\t{$src, ${dst} {${mask}} {z}|" #
35483547
"${dst} {${mask}} {z}, $src}",
35493548
[], _.ExeDomain>, EVEX, EVEX_KZ,
3550-
FoldGenData<BaseName#_.ZSuffix#rrkz>,
35513549
Sched<[Sched.RR]>;
35523550
}
35533551

@@ -4535,7 +4533,6 @@ let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in {
45354533
(ins VR128X:$src1, VR128X:$src2),
45364534
"vmovsh\t{$src2, $src1, $dst|$dst, $src1, $src2}",
45374535
[]>, T_MAP5XS, EVEX_4V, VEX_LIG,
4538-
FoldGenData<"VMOVSHZrr">,
45394536
Sched<[SchedWriteFShuffle.XMM]>;
45404537

45414538
let Constraints = "$src0 = $dst" in
@@ -4545,22 +4542,19 @@ let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in {
45454542
"vmovsh\t{$src2, $src1, $dst {${mask}}|"#
45464543
"$dst {${mask}}, $src1, $src2}",
45474544
[]>, T_MAP5XS, EVEX_K, EVEX_4V, VEX_LIG,
4548-
FoldGenData<"VMOVSHZrrk">,
45494545
Sched<[SchedWriteFShuffle.XMM]>;
45504546

45514547
def VMOVSHZrrkz_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst),
45524548
(ins f16x_info.KRCWM:$mask, VR128X:$src1, VR128X:$src2),
45534549
"vmovsh\t{$src2, $src1, $dst {${mask}} {z}|"#
45544550
"$dst {${mask}} {z}, $src1, $src2}",
45554551
[]>, EVEX_KZ, T_MAP5XS, EVEX_4V, VEX_LIG,
4556-
FoldGenData<"VMOVSHZrrkz">,
45574552
Sched<[SchedWriteFShuffle.XMM]>;
45584553
}
45594554
def VMOVSSZrr_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst),
45604555
(ins VR128X:$src1, VR128X:$src2),
45614556
"vmovss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
45624557
[]>, XS, EVEX_4V, VEX_LIG,
4563-
FoldGenData<"VMOVSSZrr">,
45644558
Sched<[SchedWriteFShuffle.XMM]>;
45654559

45664560
let Constraints = "$src0 = $dst" in
@@ -4570,22 +4564,19 @@ let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in {
45704564
"vmovss\t{$src2, $src1, $dst {${mask}}|"#
45714565
"$dst {${mask}}, $src1, $src2}",
45724566
[]>, EVEX_K, XS, EVEX_4V, VEX_LIG,
4573-
FoldGenData<"VMOVSSZrrk">,
45744567
Sched<[SchedWriteFShuffle.XMM]>;
45754568

45764569
def VMOVSSZrrkz_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst),
45774570
(ins f32x_info.KRCWM:$mask, VR128X:$src1, VR128X:$src2),
45784571
"vmovss\t{$src2, $src1, $dst {${mask}} {z}|"#
45794572
"$dst {${mask}} {z}, $src1, $src2}",
45804573
[]>, EVEX_KZ, XS, EVEX_4V, VEX_LIG,
4581-
FoldGenData<"VMOVSSZrrkz">,
45824574
Sched<[SchedWriteFShuffle.XMM]>;
45834575

45844576
def VMOVSDZrr_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst),
45854577
(ins VR128X:$src1, VR128X:$src2),
45864578
"vmovsd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
45874579
[]>, XD, EVEX_4V, VEX_LIG, REX_W,
4588-
FoldGenData<"VMOVSDZrr">,
45894580
Sched<[SchedWriteFShuffle.XMM]>;
45904581

45914582
let Constraints = "$src0 = $dst" in
@@ -4595,17 +4586,15 @@ let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in {
45954586
"vmovsd\t{$src2, $src1, $dst {${mask}}|"#
45964587
"$dst {${mask}}, $src1, $src2}",
45974588
[]>, EVEX_K, XD, EVEX_4V, VEX_LIG,
4598-
REX_W, FoldGenData<"VMOVSDZrrk">,
4599-
Sched<[SchedWriteFShuffle.XMM]>;
4589+
REX_W, Sched<[SchedWriteFShuffle.XMM]>;
46004590

46014591
def VMOVSDZrrkz_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst),
46024592
(ins f64x_info.KRCWM:$mask, VR128X:$src1,
46034593
VR128X:$src2),
46044594
"vmovsd\t{$src2, $src1, $dst {${mask}} {z}|"#
46054595
"$dst {${mask}} {z}, $src1, $src2}",
46064596
[]>, EVEX_KZ, XD, EVEX_4V, VEX_LIG,
4607-
REX_W, FoldGenData<"VMOVSDZrrkz">,
4608-
Sched<[SchedWriteFShuffle.XMM]>;
4597+
REX_W, Sched<[SchedWriteFShuffle.XMM]>;
46094598
}
46104599

46114600
def : InstAlias<"vmovsh.s\t{$src2, $src1, $dst|$dst, $src1, $src2}",
@@ -11648,8 +11637,7 @@ multiclass avx512_extract_elt_w<string OpcodeStr, X86VectorVTInfo _> {
1164811637
def rr_REV : AVX512Ii8<0x15, MRMDestReg, (outs GR32orGR64:$dst),
1164911638
(ins _.RC:$src1, u8imm:$src2),
1165011639
OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
11651-
EVEX, TAPD, FoldGenData<NAME#rr>,
11652-
Sched<[WriteVecExtract]>;
11640+
EVEX, TAPD, Sched<[WriteVecExtract]>;
1165311641

1165411642
defm NAME : avx512_extract_elt_bw_m<0x15, OpcodeStr, X86pextrw, _>, TAPD;
1165511643
}

‎llvm/lib/Target/X86/X86InstrArithmetic.td

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -881,10 +881,10 @@ multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
881881
} // isConvertibleToThreeAddress
882882
} // isCommutable
883883

884-
def NAME#8rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi8>, FoldGenData<NAME#8rr>;
885-
def NAME#16rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi16>, FoldGenData<NAME#16rr>;
886-
def NAME#32rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi32>, FoldGenData<NAME#32rr>;
887-
def NAME#64rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi64>, FoldGenData<NAME#64rr>;
884+
def NAME#8rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi8>;
885+
def NAME#16rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi16>;
886+
def NAME#32rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi32>;
887+
def NAME#64rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi64>;
888888

889889
def NAME#8rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi8 , opnodeflag>;
890890
def NAME#16rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi16, opnodeflag>;
@@ -968,10 +968,10 @@ multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
968968
} // isConvertibleToThreeAddress
969969
} // isCommutable
970970

971-
def NAME#8rr_REV : BinOpRR_RFF_Rev<BaseOpc2, mnemonic, Xi8>, FoldGenData<NAME#8rr>;
972-
def NAME#16rr_REV : BinOpRR_RFF_Rev<BaseOpc2, mnemonic, Xi16>, FoldGenData<NAME#16rr>;
973-
def NAME#32rr_REV : BinOpRR_RFF_Rev<BaseOpc2, mnemonic, Xi32>, FoldGenData<NAME#32rr>;
974-
def NAME#64rr_REV : BinOpRR_RFF_Rev<BaseOpc2, mnemonic, Xi64>, FoldGenData<NAME#64rr>;
971+
def NAME#8rr_REV : BinOpRR_RFF_Rev<BaseOpc2, mnemonic, Xi8>;
972+
def NAME#16rr_REV : BinOpRR_RFF_Rev<BaseOpc2, mnemonic, Xi16>;
973+
def NAME#32rr_REV : BinOpRR_RFF_Rev<BaseOpc2, mnemonic, Xi32>;
974+
def NAME#64rr_REV : BinOpRR_RFF_Rev<BaseOpc2, mnemonic, Xi64>;
975975

976976
def NAME#8rm : BinOpRM_RFF<BaseOpc2, mnemonic, Xi8 , opnode>;
977977
def NAME#16rm : BinOpRM_RFF<BaseOpc2, mnemonic, Xi16, opnode>;
@@ -1050,10 +1050,10 @@ multiclass ArithBinOp_F<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
10501050
}
10511051
} // isCommutable
10521052

1053-
def NAME#8rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi8>, FoldGenData<NAME#8rr>;
1054-
def NAME#16rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi16>, FoldGenData<NAME#16rr>;
1055-
def NAME#32rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi32>, FoldGenData<NAME#32rr>;
1056-
def NAME#64rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi64>, FoldGenData<NAME#64rr>;
1053+
def NAME#8rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi8>;
1054+
def NAME#16rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi16>;
1055+
def NAME#32rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi32>;
1056+
def NAME#64rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi64>;
10571057

10581058
def NAME#8rm : BinOpRM_F<BaseOpc2, mnemonic, Xi8 , opnode>;
10591059
def NAME#16rm : BinOpRM_F<BaseOpc2, mnemonic, Xi16, opnode>;

‎llvm/lib/Target/X86/X86InstrFMA.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -423,7 +423,7 @@ let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
423423
(ins RC:$src1, RC:$src2, RC:$src3),
424424
!strconcat(OpcodeStr,
425425
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>,
426-
VEX_LIG, FoldGenData<NAME#rr>, Sched<[sched]>;
426+
VEX_LIG, Sched<[sched]>;
427427
}
428428

429429
multiclass fma4s_int<bits<8> opc, string OpcodeStr, Operand memop,
@@ -458,7 +458,7 @@ let isCodeGenOnly = 1, hasSideEffects = 0,
458458
(ins VR128:$src1, VR128:$src2, VR128:$src3),
459459
!strconcat(OpcodeStr,
460460
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
461-
[]>, VEX_LIG, FoldGenData<NAME#rr_Int>, Sched<[sched]>;
461+
[]>, VEX_LIG, Sched<[sched]>;
462462
} // isCodeGenOnly = 1
463463
}
464464

@@ -527,12 +527,12 @@ let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
527527
(ins VR128:$src1, VR128:$src2, VR128:$src3),
528528
!strconcat(OpcodeStr,
529529
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>,
530-
Sched<[sched.XMM]>, FoldGenData<NAME#rr>;
530+
Sched<[sched.XMM]>;
531531
def Yrr_REV : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
532532
(ins VR256:$src1, VR256:$src2, VR256:$src3),
533533
!strconcat(OpcodeStr,
534534
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>,
535-
VEX_L, Sched<[sched.YMM]>, FoldGenData<NAME#Yrr>;
535+
VEX_L, Sched<[sched.YMM]>;
536536
} // isCodeGenOnly = 1
537537
}
538538

‎llvm/lib/Target/X86/X86InstrFormats.td

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -259,12 +259,6 @@ class EVEX_CD8<int esize, CD8VForm form> {
259259
class XOP { Encoding OpEnc = EncXOP; }
260260
class XOP_4V : XOP { bit hasVEX_4V = 1; }
261261

262-
// Specify the alternative register form instruction to replace the current
263-
// instruction in case it was picked during generation of memory folding tables
264-
class FoldGenData<string _RegisterForm> {
265-
string FoldGenRegForm = _RegisterForm;
266-
}
267-
268262
// Provide a specific instruction to be used by the EVEX2VEX conversion.
269263
class EVEX2VEXOverride<string VEXInstrName> {
270264
string EVEX2VEXOverride = VEXInstrName;
@@ -352,10 +346,6 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
352346
CD8_EltSize,
353347
!srl(VectSize, CD8_Form{1-0}))), 0);
354348

355-
// Used in the memory folding generation (TableGen backend) to point to an alternative
356-
// instruction to replace the current one in case it got picked during generation.
357-
string FoldGenRegForm = ?;
358-
359349
// Used to prevent an explicit EVEX2VEX override for this instruction.
360350
string EVEX2VEXOverride = ?;
361351

‎llvm/lib/Target/X86/X86InstrMMX.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -178,7 +178,7 @@ def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR64:$src),
178178
"movd\t{$src, $dst|$dst, $src}",
179179
[(set GR32:$dst,
180180
(MMX_X86movd2w (x86mmx VR64:$src)))]>,
181-
Sched<[WriteVecMoveToGpr]>, FoldGenData<"MMX_MOVD64rr">;
181+
Sched<[WriteVecMoveToGpr]>;
182182

183183
let isBitcast = 1 in
184184
def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),

‎llvm/lib/Target/X86/X86InstrMisc.td

Lines changed: 7 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -374,14 +374,11 @@ def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
374374
// Longer forms that use a ModR/M byte. Needed for disassembler
375375
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
376376
def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src),
377-
"mov{b}\t{$src, $dst|$dst, $src}", []>,
378-
FoldGenData<"MOV8ri">;
377+
"mov{b}\t{$src, $dst|$dst, $src}", []>;
379378
def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src),
380-
"mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16,
381-
FoldGenData<"MOV16ri">;
379+
"mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
382380
def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src),
383-
"mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32,
384-
FoldGenData<"MOV32ri">;
381+
"mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
385382
}
386383
} // SchedRW
387384

@@ -523,17 +520,13 @@ def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs), (ins offset64_64:$dst),
523520
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
524521
SchedRW = [WriteMove], isMoveReg = 1 in {
525522
def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
526-
"mov{b}\t{$src, $dst|$dst, $src}", []>,
527-
FoldGenData<"MOV8rr">;
523+
"mov{b}\t{$src, $dst|$dst, $src}", []>;
528524
def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
529-
"mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16,
530-
FoldGenData<"MOV16rr">;
525+
"mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
531526
def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
532-
"mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32,
533-
FoldGenData<"MOV32rr">;
527+
"mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
534528
def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
535-
"mov{q}\t{$src, $dst|$dst, $src}", []>,
536-
FoldGenData<"MOV64rr">;
529+
"mov{q}\t{$src, $dst|$dst, $src}", []>;
537530
}
538531

539532
let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {

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