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[X86] Add missing immediate qualifier to the (V)PCLMULQDQ instruction names
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6 files changed

+39
-39
lines changed

6 files changed

+39
-39
lines changed

‎llvm/lib/Target/X86/X86InstrInfo.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2491,12 +2491,12 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
24912491
WorkingMI->removeOperand(3);
24922492
break;
24932493
}
2494-
case X86::PCLMULQDQrr:
2495-
case X86::VPCLMULQDQrr:
2496-
case X86::VPCLMULQDQYrr:
2497-
case X86::VPCLMULQDQZrr:
2498-
case X86::VPCLMULQDQZ128rr:
2499-
case X86::VPCLMULQDQZ256rr: {
2494+
case X86::PCLMULQDQrri:
2495+
case X86::VPCLMULQDQrri:
2496+
case X86::VPCLMULQDQYrri:
2497+
case X86::VPCLMULQDQZrri:
2498+
case X86::VPCLMULQDQZ128rri:
2499+
case X86::VPCLMULQDQZ256rri: {
25002500
// SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
25012501
// SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
25022502
unsigned Imm = MI.getOperand(3).getImm();

‎llvm/lib/Target/X86/X86InstrSSE.td

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -6917,14 +6917,14 @@ def PCLMULCommuteImm : SDNodeXForm<timm, [{
69176917
let Predicates = [NoAVX, HasPCLMUL] in {
69186918
let Constraints = "$src1 = $dst" in {
69196919
let isCommutable = 1 in
6920-
def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
6920+
def PCLMULQDQrri : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
69216921
(ins VR128:$src1, VR128:$src2, u8imm:$src3),
69226922
"pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
69236923
[(set VR128:$dst,
69246924
(int_x86_pclmulqdq VR128:$src1, VR128:$src2, timm:$src3))]>,
69256925
Sched<[WriteCLMul]>;
69266926

6927-
def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
6927+
def PCLMULQDQrmi : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
69286928
(ins VR128:$src1, i128mem:$src2, u8imm:$src3),
69296929
"pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
69306930
[(set VR128:$dst,
@@ -6935,44 +6935,44 @@ let Predicates = [NoAVX, HasPCLMUL] in {
69356935

69366936
def : Pat<(int_x86_pclmulqdq (memop addr:$src2), VR128:$src1,
69376937
(i8 timm:$src3)),
6938-
(PCLMULQDQrm VR128:$src1, addr:$src2,
6938+
(PCLMULQDQrmi VR128:$src1, addr:$src2,
69396939
(PCLMULCommuteImm timm:$src3))>;
69406940
} // Predicates = [NoAVX, HasPCLMUL]
69416941

69426942
// SSE aliases
69436943
foreach HI = ["hq","lq"] in
69446944
foreach LO = ["hq","lq"] in {
69456945
def : InstAlias<"pclmul" # HI # LO # "dq\t{$src, $dst|$dst, $src}",
6946-
(PCLMULQDQrr VR128:$dst, VR128:$src,
6946+
(PCLMULQDQrri VR128:$dst, VR128:$src,
69476947
!add(!shl(!eq(LO,"hq"),4),!eq(HI,"hq"))), 0>;
69486948
def : InstAlias<"pclmul" # HI # LO # "dq\t{$src, $dst|$dst, $src}",
6949-
(PCLMULQDQrm VR128:$dst, i128mem:$src,
6949+
(PCLMULQDQrmi VR128:$dst, i128mem:$src,
69506950
!add(!shl(!eq(LO,"hq"),4),!eq(HI,"hq"))), 0>;
69516951
}
69526952

69536953
// AVX carry-less Multiplication instructions
69546954
multiclass vpclmulqdq<RegisterClass RC, X86MemOperand MemOp,
69556955
PatFrag LdFrag, Intrinsic IntId> {
69566956
let isCommutable = 1 in
6957-
def rr : PCLMULIi8<0x44, MRMSrcReg, (outs RC:$dst),
6958-
(ins RC:$src1, RC:$src2, u8imm:$src3),
6959-
"vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6960-
[(set RC:$dst,
6961-
(IntId RC:$src1, RC:$src2, timm:$src3))]>,
6962-
Sched<[WriteCLMul]>;
6963-
6964-
def rm : PCLMULIi8<0x44, MRMSrcMem, (outs RC:$dst),
6965-
(ins RC:$src1, MemOp:$src2, u8imm:$src3),
6966-
"vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6967-
[(set RC:$dst,
6968-
(IntId RC:$src1, (LdFrag addr:$src2), timm:$src3))]>,
6969-
Sched<[WriteCLMul.Folded, WriteCLMul.ReadAfterFold]>;
6957+
def rri : PCLMULIi8<0x44, MRMSrcReg, (outs RC:$dst),
6958+
(ins RC:$src1, RC:$src2, u8imm:$src3),
6959+
"vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6960+
[(set RC:$dst,
6961+
(IntId RC:$src1, RC:$src2, timm:$src3))]>,
6962+
Sched<[WriteCLMul]>;
6963+
6964+
def rmi : PCLMULIi8<0x44, MRMSrcMem, (outs RC:$dst),
6965+
(ins RC:$src1, MemOp:$src2, u8imm:$src3),
6966+
"vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6967+
[(set RC:$dst,
6968+
(IntId RC:$src1, (LdFrag addr:$src2), timm:$src3))]>,
6969+
Sched<[WriteCLMul.Folded, WriteCLMul.ReadAfterFold]>;
69706970

69716971
// We can commute a load in the first operand by swapping the sources and
69726972
// rotating the immediate.
69736973
def : Pat<(IntId (LdFrag addr:$src2), RC:$src1, (i8 timm:$src3)),
6974-
(!cast<Instruction>(NAME#"rm") RC:$src1, addr:$src2,
6975-
(PCLMULCommuteImm timm:$src3))>;
6974+
(!cast<Instruction>(NAME#"rmi") RC:$src1, addr:$src2,
6975+
(PCLMULCommuteImm timm:$src3))>;
69766976
}
69776977

69786978
let Predicates = [HasAVX, NoVLX_Or_NoVPCLMULQDQ, HasPCLMUL] in
@@ -6986,10 +6986,10 @@ defm VPCLMULQDQY : vpclmulqdq<VR256, i256mem, load,
69866986
multiclass vpclmulqdq_aliases_impl<string InstStr, RegisterClass RC,
69876987
X86MemOperand MemOp, string Hi, string Lo> {
69886988
def : InstAlias<"vpclmul"#Hi#Lo#"dq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6989-
(!cast<Instruction>(InstStr # "rr") RC:$dst, RC:$src1, RC:$src2,
6989+
(!cast<Instruction>(InstStr # "rri") RC:$dst, RC:$src1, RC:$src2,
69906990
!add(!shl(!eq(Lo,"hq"),4),!eq(Hi,"hq"))), 0>;
69916991
def : InstAlias<"vpclmul"#Hi#Lo#"dq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6992-
(!cast<Instruction>(InstStr # "rm") RC:$dst, RC:$src1, MemOp:$src2,
6992+
(!cast<Instruction>(InstStr # "rmi") RC:$dst, RC:$src1, MemOp:$src2,
69936993
!add(!shl(!eq(Lo,"hq"),4),!eq(Hi,"hq"))), 0>;
69946994
}
69956995

‎llvm/lib/Target/X86/X86SchedAlderlakeP.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2295,7 +2295,7 @@ def ADLPWriteResGroup263 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
22952295
}
22962296
def : InstRW<[ADLPWriteResGroup263, ReadAfterVecYLd], (instregex "^VPACK(S|U)S(DW|WB)Yrm$")>;
22972297
def : InstRW<[ADLPWriteResGroup263, ReadAfterVecYLd], (instrs VPCMPGTQYrm)>;
2298-
def : InstRW<[ADLPWriteResGroup263, ReadAfterVecXLd], (instrs VPCLMULQDQYrm)>;
2298+
def : InstRW<[ADLPWriteResGroup263, ReadAfterVecXLd], (instrs VPCLMULQDQYrmi)>;
22992299

23002300
def ADLPWriteResGroup264 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_11]> {
23012301
let Latency = 9;

‎llvm/lib/Target/X86/X86SchedSapphireRapids.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2665,8 +2665,8 @@ def : InstRW<[SPRWriteResGroup258, ReadAfterVecYLd], (instregex "^VALIGN(D|Q)Z((
26652665
"^VPUNPCK(H|L)(BW|WD)Zrmk(z?)$")>;
26662666
def : InstRW<[SPRWriteResGroup258, ReadAfterVecYLd], (instrs VPCMPGTQYrm)>;
26672667
def : InstRW<[SPRWriteResGroup258, ReadAfterVecXLd], (instregex "^VPALIGNRZ128rmik(z?)$",
2668-
"^VPCLMULQDQ(Y|Z)rm$")>;
2669-
def : InstRW<[SPRWriteResGroup258, ReadAfterVecXLd], (instrs VPCLMULQDQZ256rm)>;
2668+
"^VPCLMULQDQ(Y|Z)rmi$")>;
2669+
def : InstRW<[SPRWriteResGroup258, ReadAfterVecXLd], (instrs VPCLMULQDQZ256rmi)>;
26702670

26712671
def SPRWriteResGroup259 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11]> {
26722672
let ReleaseAtCycles = [3, 1];

‎llvm/lib/Target/X86/X86ScheduleBdVer2.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1275,12 +1275,12 @@ def : InstRW<[WritePHAdd.Folded], (instrs PHADDDrm, PHSUBDrm,
12751275

12761276
defm : PdWriteResXMMPair<WriteCLMul, [PdFPU0, PdFPMMA], 12, [1, 7], 5, 1>;
12771277

1278-
def PdWriteVPCLMULQDQrr : SchedWriteRes<[PdFPU0, PdFPMMA]> {
1278+
def PdWriteVPCLMULQDQrri : SchedWriteRes<[PdFPU0, PdFPMMA]> {
12791279
let Latency = 12;
12801280
let ReleaseAtCycles = [1, 7];
12811281
let NumMicroOps = 6;
12821282
}
1283-
def : InstRW<[PdWriteVPCLMULQDQrr], (instrs VPCLMULQDQrr)>;
1283+
def : InstRW<[PdWriteVPCLMULQDQrri], (instrs VPCLMULQDQrri)>;
12841284

12851285
////////////////////////////////////////////////////////////////////////////////
12861286
// SSE4A instructions.

‎llvm/test/TableGen/x86-fold-tables.inc

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2129,7 +2129,7 @@ static const X86FoldTableEntry Table2[] = {
21292129
{X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16},
21302130
{X86::PBLENDVBrr0, X86::PBLENDVBrm0, TB_ALIGN_16},
21312131
{X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16},
2132-
{X86::PCLMULQDQrr, X86::PCLMULQDQrm, TB_ALIGN_16},
2132+
{X86::PCLMULQDQrri, X86::PCLMULQDQrmi, TB_ALIGN_16},
21332133
{X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16},
21342134
{X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16},
21352135
{X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16},
@@ -3058,11 +3058,11 @@ static const X86FoldTableEntry Table2[] = {
30583058
{X86::VPBROADCASTWZ128rrkz, X86::VPBROADCASTWZ128rmkz, TB_NO_REVERSE},
30593059
{X86::VPBROADCASTWZ256rrkz, X86::VPBROADCASTWZ256rmkz, TB_NO_REVERSE},
30603060
{X86::VPBROADCASTWZrrkz, X86::VPBROADCASTWZrmkz, TB_NO_REVERSE},
3061-
{X86::VPCLMULQDQYrr, X86::VPCLMULQDQYrm, 0},
3062-
{X86::VPCLMULQDQZ128rr, X86::VPCLMULQDQZ128rm, 0},
3063-
{X86::VPCLMULQDQZ256rr, X86::VPCLMULQDQZ256rm, 0},
3064-
{X86::VPCLMULQDQZrr, X86::VPCLMULQDQZrm, 0},
3065-
{X86::VPCLMULQDQrr, X86::VPCLMULQDQrm, 0},
3061+
{X86::VPCLMULQDQYrri, X86::VPCLMULQDQYrmi, 0},
3062+
{X86::VPCLMULQDQZ128rri, X86::VPCLMULQDQZ128rmi, 0},
3063+
{X86::VPCLMULQDQZ256rri, X86::VPCLMULQDQZ256rmi, 0},
3064+
{X86::VPCLMULQDQZrri, X86::VPCLMULQDQZrmi, 0},
3065+
{X86::VPCLMULQDQrri, X86::VPCLMULQDQrmi, 0},
30663066
{X86::VPCMOVYrrr, X86::VPCMOVYrmr, 0},
30673067
{X86::VPCMOVrrr, X86::VPCMOVrmr, 0},
30683068
{X86::VPCMPBZ128rri, X86::VPCMPBZ128rmi, 0},

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