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[Clang][AArch64] Add diagnostics for builtins that use ZT0. (#79140)
Similar to what we did for ZA, this patch adds diagnostics to flag when using a ZT0 builtin in a function that does not have ZT0 state.
1 parent d3a6a90 commit 1f6f199

15 files changed

+122
-76
lines changed

‎clang/include/clang/Basic/DiagnosticSemaKinds.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3170,6 +3170,9 @@ def warn_attribute_arm_sm_incompat_builtin : Warning<
31703170
def warn_attribute_arm_za_builtin_no_za_state : Warning<
31713171
"builtin call is not valid when calling from a function without active ZA state">,
31723172
InGroup<DiagGroup<"undefined-arm-za">>;
3173+
def warn_attribute_arm_zt0_builtin_no_zt0_state : Warning<
3174+
"builtin call is not valid when calling from a function without active ZT0 state">,
3175+
InGroup<DiagGroup<"undefined-arm-zt0">>;
31733176
def err_sve_vector_in_non_sve_target : Error<
31743177
"SVE vector type %0 cannot be used in a target without sve">;
31753178
def err_attribute_riscv_rvv_bits_unsupported : Error<

‎clang/include/clang/Basic/arm_sme.td

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -636,37 +636,37 @@ let TargetGuard = "sme2,sme-i16i64" in {
636636
// Spill and fill of ZT0
637637
//
638638
let TargetGuard = "sme2" in {
639-
def SVLDR_ZT : Inst<"svldr_zt", "viQ", "", MergeNone, "aarch64_sme_ldr_zt", [IsOverloadNone, IsStreamingCompatible], [ImmCheck<0, ImmCheck0_0>]>;
640-
def SVSTR_ZT : Inst<"svstr_zt", "vi%", "", MergeNone, "aarch64_sme_str_zt", [IsOverloadNone, IsStreamingCompatible], [ImmCheck<0, ImmCheck0_0>]>;
639+
def SVLDR_ZT : Inst<"svldr_zt", "viQ", "", MergeNone, "aarch64_sme_ldr_zt", [IsOverloadNone, IsStreamingCompatible, IsInOutZT0], [ImmCheck<0, ImmCheck0_0>]>;
640+
def SVSTR_ZT : Inst<"svstr_zt", "vi%", "", MergeNone, "aarch64_sme_str_zt", [IsOverloadNone, IsStreamingCompatible, IsInZT0], [ImmCheck<0, ImmCheck0_0>]>;
641641
}
642642

643643
//
644644
// Zero ZT0
645645
//
646646
let TargetGuard = "sme2" in {
647-
def SVZERO_ZT : Inst<"svzero_zt", "vi", "", MergeNone, "aarch64_sme_zero_zt", [IsOverloadNone, IsStreamingCompatible], [ImmCheck<0, ImmCheck0_0>]>;
647+
def SVZERO_ZT : Inst<"svzero_zt", "vi", "", MergeNone, "aarch64_sme_zero_zt", [IsOverloadNone, IsStreamingCompatible, IsOutZT0], [ImmCheck<0, ImmCheck0_0>]>;
648648
}
649649

650650
//
651651
// lookup table expand four contiguous registers
652652
//
653653
let TargetGuard = "sme2" in {
654-
def SVLUTI2_LANE_ZT_X4 : Inst<"svluti2_lane_zt_{d}_x4", "4.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x4", [IsStreaming], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>;
655-
def SVLUTI4_LANE_ZT_X4 : Inst<"svluti4_lane_zt_{d}_x4", "4.di[i", "sUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x4", [IsStreaming], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_1>]>;
654+
def SVLUTI2_LANE_ZT_X4 : Inst<"svluti2_lane_zt_{d}_x4", "4.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x4", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>;
655+
def SVLUTI4_LANE_ZT_X4 : Inst<"svluti4_lane_zt_{d}_x4", "4.di[i", "sUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x4", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_1>]>;
656656
}
657657

658658
//
659659
// lookup table expand one register
660660
//
661661
let TargetGuard = "sme2" in {
662-
def SVLUTI2_LANE_ZT : Inst<"svluti2_lane_zt_{d}", "di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt", [IsStreaming], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_15>]>;
663-
def SVLUTI4_LANE_ZT : Inst<"svluti4_lane_zt_{d}", "di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt", [IsStreaming], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
662+
def SVLUTI2_LANE_ZT : Inst<"svluti2_lane_zt_{d}", "di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_15>]>;
663+
def SVLUTI4_LANE_ZT : Inst<"svluti4_lane_zt_{d}", "di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
664664
}
665665

666666
//
667667
// lookup table expand two contiguous registers
668668
//
669669
let TargetGuard = "sme2" in {
670-
def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
671-
def SVLUTI4_LANE_ZT_X2 : Inst<"svluti4_lane_zt_{d}_x2", "2.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x2", [IsStreaming], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>;
670+
def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
671+
def SVLUTI4_LANE_ZT_X2 : Inst<"svluti4_lane_zt_{d}_x2", "2.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x2", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>;
672672
}

‎clang/include/clang/Basic/arm_sve_sme_incl.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -229,6 +229,9 @@ def IsStreamingOrSVE2p1 : FlagType<0x40000000000>; // Use for intrin
229229
def IsInZA : FlagType<0x80000000000>;
230230
def IsOutZA : FlagType<0x100000000000>;
231231
def IsInOutZA : FlagType<0x200000000000>;
232+
def IsInZT0 : FlagType<0x400000000000>;
233+
def IsOutZT0 : FlagType<0x800000000000>;
234+
def IsInOutZT0 : FlagType<0x1000000000000>;
232235

233236
// These must be kept in sync with the flags in include/clang/Basic/TargetBuiltins.h
234237
class ImmCheckType<int val> {

‎clang/lib/Sema/SemaChecking.cpp

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3013,6 +3013,11 @@ enum ArmSMEState : unsigned {
30133013
ArmOutZA = 0b10,
30143014
ArmInOutZA = 0b11,
30153015
ArmZAMask = 0b11,
3016+
3017+
ArmInZT0 = 0b01 << 2,
3018+
ArmOutZT0 = 0b10 << 2,
3019+
ArmInOutZT0 = 0b11 << 2,
3020+
ArmZT0Mask = 0b11 << 2
30163021
};
30173022

30183023
bool Sema::ParseSVEImmChecks(
@@ -3206,6 +3211,13 @@ static bool hasArmZAState(const FunctionDecl *FD) {
32063211
(FD->hasAttr<ArmNewAttr>() && FD->getAttr<ArmNewAttr>()->isNewZA());
32073212
}
32083213

3214+
static bool hasArmZT0State(const FunctionDecl *FD) {
3215+
const auto *T = FD->getType()->getAs<FunctionProtoType>();
3216+
return (T && FunctionType::getArmZT0State(T->getAArch64SMEAttributes()) !=
3217+
FunctionType::ARM_None) ||
3218+
(FD->hasAttr<ArmNewAttr>() && FD->getAttr<ArmNewAttr>()->isNewZT0());
3219+
}
3220+
32093221
static ArmSMEState getSMEState(unsigned BuiltinID) {
32103222
switch (BuiltinID) {
32113223
default:
@@ -3233,6 +3245,11 @@ bool Sema::CheckSMEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
32333245
Diag(TheCall->getBeginLoc(),
32343246
diag::warn_attribute_arm_za_builtin_no_za_state)
32353247
<< TheCall->getSourceRange();
3248+
3249+
if ((getSMEState(BuiltinID) & ArmZT0Mask) && !hasArmZT0State(FD))
3250+
Diag(TheCall->getBeginLoc(),
3251+
diag::warn_attribute_arm_zt0_builtin_no_zt0_state)
3252+
<< TheCall->getSourceRange();
32363253
}
32373254

32383255
// Range check SME intrinsics that take immediate values.

‎clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ldr_str_zt.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@
2020
// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sme.ldr.zt(i32 0, ptr [[BASE:%.*]])
2121
// CPP-CHECK-NEXT: ret void
2222
//
23-
void test_svldr_zt(const void *base) __arm_streaming_compatible __arm_out("za") {
23+
void test_svldr_zt(const void *base) __arm_streaming_compatible __arm_out("zt0") {
2424
svldr_zt(0, base);
2525
}
2626

@@ -36,6 +36,6 @@ void test_svldr_zt(const void *base) __arm_streaming_compatible __arm_out("za")
3636
// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sme.str.zt(i32 0, ptr [[BASE:%.*]])
3737
// CPP-CHECK-NEXT: ret void
3838
//
39-
void test_svstr_zt(void *base) __arm_streaming_compatible __arm_in("za") {
39+
void test_svstr_zt(void *base) __arm_streaming_compatible __arm_in("zt0") {
4040
svstr_zt(0, base);
4141
}

‎clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt.c

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@
1919
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> [[ZN:%.*]], i32 15)
2020
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
2121
//
22-
svuint8_t test_svluti2_lane_zt_u8(svuint8_t zn) __arm_streaming __arm_in("za") {
22+
svuint8_t test_svluti2_lane_zt_u8(svuint8_t zn) __arm_streaming __arm_in("zt0") {
2323
return svluti2_lane_zt_u8(0, zn, 15);
2424
}
2525

@@ -34,7 +34,7 @@ svuint8_t test_svluti2_lane_zt_u8(svuint8_t zn) __arm_streaming __arm_in("za") {
3434
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sme.luti2.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> [[ZN:%.*]], i32 15)
3535
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
3636
//
37-
svint8_t test_svluti2_lane_zt_s8(svuint8_t zn) __arm_streaming __arm_in("za") {
37+
svint8_t test_svluti2_lane_zt_s8(svuint8_t zn) __arm_streaming __arm_in("zt0") {
3838
return svluti2_lane_zt_s8(0, zn, 15);
3939
}
4040

@@ -48,7 +48,7 @@ svint8_t test_svluti2_lane_zt_s8(svuint8_t zn) __arm_streaming __arm_in("za") {
4848
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 0, <vscale x 16 x i8> [[ZN:%.*]], i32 15)
4949
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
5050
//
51-
svuint16_t test_svluti2_lane_zt_u16(svuint8_t zn) __arm_streaming __arm_in("za") {
51+
svuint16_t test_svluti2_lane_zt_u16(svuint8_t zn) __arm_streaming __arm_in("zt0") {
5252
return svluti2_lane_zt_u16(0, zn, 15);
5353
}
5454

@@ -63,7 +63,7 @@ svuint16_t test_svluti2_lane_zt_u16(svuint8_t zn) __arm_streaming __arm_in("za")
6363
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sme.luti2.lane.zt.nxv8i16(i32 0, <vscale x 16 x i8> [[ZN:%.*]], i32 15)
6464
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
6565
//
66-
svint16_t test_svluti2_lane_zt_s16(svuint8_t zn) __arm_streaming __arm_in("za") {
66+
svint16_t test_svluti2_lane_zt_s16(svuint8_t zn) __arm_streaming __arm_in("zt0") {
6767
return svluti2_lane_zt_s16(0, zn, 15);
6868
}
6969

@@ -77,7 +77,7 @@ svint16_t test_svluti2_lane_zt_s16(svuint8_t zn) __arm_streaming __arm_in("za")
7777
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sme.luti2.lane.zt.nxv8f16(i32 0, <vscale x 16 x i8> [[ZN:%.*]], i32 15)
7878
// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
7979
//
80-
svfloat16_t test_svluti2_lane_zt_f16(svuint8_t zn) __arm_streaming __arm_in("za") {
80+
svfloat16_t test_svluti2_lane_zt_f16(svuint8_t zn) __arm_streaming __arm_in("zt0") {
8181
return svluti2_lane_zt_f16(0, zn, 15);
8282
}
8383

@@ -91,7 +91,7 @@ svfloat16_t test_svluti2_lane_zt_f16(svuint8_t zn) __arm_streaming __arm_in("za"
9191
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x bfloat> @llvm.aarch64.sme.luti2.lane.zt.nxv8bf16(i32 0, <vscale x 16 x i8> [[ZN:%.*]], i32 15)
9292
// CPP-CHECK-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
9393
//
94-
svbfloat16_t test_svluti2_lane_zt_bf16(svuint8_t zn) __arm_streaming __arm_in("za") {
94+
svbfloat16_t test_svluti2_lane_zt_bf16(svuint8_t zn) __arm_streaming __arm_in("zt0") {
9595
return svluti2_lane_zt_bf16(0, zn, 15);
9696
}
9797

@@ -105,7 +105,7 @@ svbfloat16_t test_svluti2_lane_zt_bf16(svuint8_t zn) __arm_streaming __arm_in("z
105105
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 0, <vscale x 16 x i8> [[ZN:%.*]], i32 15)
106106
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
107107
//
108-
svuint32_t test_svluti2_lane_zt_u32(svuint8_t zn) __arm_streaming __arm_in("za") {
108+
svuint32_t test_svluti2_lane_zt_u32(svuint8_t zn) __arm_streaming __arm_in("zt0") {
109109
return svluti2_lane_zt_u32(0, zn, 15);
110110
}
111111

@@ -119,7 +119,7 @@ svuint32_t test_svluti2_lane_zt_u32(svuint8_t zn) __arm_streaming __arm_in("za")
119119
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sme.luti2.lane.zt.nxv4i32(i32 0, <vscale x 16 x i8> [[ZN:%.*]], i32 15)
120120
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
121121
//
122-
svint32_t test_svluti2_lane_zt_s32(svuint8_t zn) __arm_streaming __arm_in("za") {
122+
svint32_t test_svluti2_lane_zt_s32(svuint8_t zn) __arm_streaming __arm_in("zt0") {
123123
return svluti2_lane_zt_s32(0, zn, 15);
124124
}
125125

@@ -133,6 +133,6 @@ svint32_t test_svluti2_lane_zt_s32(svuint8_t zn) __arm_streaming __arm_in("za")
133133
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sme.luti2.lane.zt.nxv4f32(i32 0, <vscale x 16 x i8> [[ZN:%.*]], i32 15)
134134
// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]
135135
//
136-
svfloat32_t test_svluti2_lane_zt_f32(svuint8_t zn) __arm_streaming __arm_in("za") {
136+
svfloat32_t test_svluti2_lane_zt_f32(svuint8_t zn) __arm_streaming __arm_in("zt0") {
137137
return svluti2_lane_zt_f32(0, zn, 15);
138138
}

‎clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@
2626
// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> [[TMP2]], <vscale x 16 x i8> [[TMP3]], i64 16)
2727
// CPP-CHECK-NEXT: ret <vscale x 32 x i8> [[TMP4]]
2828
//
29-
svuint8x2_t test_svluti2_lane_zt_u8(svuint8_t zn) __arm_streaming __arm_in("za") {
29+
svuint8x2_t test_svluti2_lane_zt_u8(svuint8_t zn) __arm_streaming __arm_in("zt0") {
3030
return svluti2_lane_zt_u8_x2(0, zn, 7);
3131
}
3232

@@ -49,7 +49,7 @@ svuint8x2_t test_svluti2_lane_zt_u8(svuint8_t zn) __arm_streaming __arm_in("za")
4949
// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call <vscale x 32 x i8> @llvm.vector.insert.nxv32i8.nxv16i8(<vscale x 32 x i8> [[TMP2]], <vscale x 16 x i8> [[TMP3]], i64 16)
5050
// CPP-CHECK-NEXT: ret <vscale x 32 x i8> [[TMP4]]
5151
//
52-
svint8x2_t test_svluti2_lane_zt_s8(svuint8_t zn) __arm_streaming __arm_in("za") {
52+
svint8x2_t test_svluti2_lane_zt_s8(svuint8_t zn) __arm_streaming __arm_in("zt0") {
5353
return svluti2_lane_zt_s8_x2(0, zn, 7);
5454
}
5555

@@ -71,7 +71,7 @@ svint8x2_t test_svluti2_lane_zt_s8(svuint8_t zn) __arm_streaming __arm_in("za")
7171
// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> [[TMP2]], <vscale x 8 x i16> [[TMP3]], i64 8)
7272
// CPP-CHECK-NEXT: ret <vscale x 16 x i16> [[TMP4]]
7373
//
74-
svuint16x2_t test_svluti2_lane_zt_u16(svuint8_t zn) __arm_streaming __arm_in("za") {
74+
svuint16x2_t test_svluti2_lane_zt_u16(svuint8_t zn) __arm_streaming __arm_in("zt0") {
7575
return svluti2_lane_zt_u16_x2(0, zn, 7);
7676
}
7777

@@ -94,7 +94,7 @@ svuint16x2_t test_svluti2_lane_zt_u16(svuint8_t zn) __arm_streaming __arm_in("za
9494
// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call <vscale x 16 x i16> @llvm.vector.insert.nxv16i16.nxv8i16(<vscale x 16 x i16> [[TMP2]], <vscale x 8 x i16> [[TMP3]], i64 8)
9595
// CPP-CHECK-NEXT: ret <vscale x 16 x i16> [[TMP4]]
9696
//
97-
svint16x2_t test_svluti2_lane_zt_s16(svuint8_t zn) __arm_streaming __arm_in("za") {
97+
svint16x2_t test_svluti2_lane_zt_s16(svuint8_t zn) __arm_streaming __arm_in("zt0") {
9898
return svluti2_lane_zt_s16_x2(0, zn, 7);
9999
}
100100

@@ -116,7 +116,7 @@ svint16x2_t test_svluti2_lane_zt_s16(svuint8_t zn) __arm_streaming __arm_in("za"
116116
// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call <vscale x 16 x half> @llvm.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> [[TMP2]], <vscale x 8 x half> [[TMP3]], i64 8)
117117
// CPP-CHECK-NEXT: ret <vscale x 16 x half> [[TMP4]]
118118
//
119-
svfloat16x2_t test_svluti2_lane_zt_f16(svuint8_t zn) __arm_streaming __arm_in("za") {
119+
svfloat16x2_t test_svluti2_lane_zt_f16(svuint8_t zn) __arm_streaming __arm_in("zt0") {
120120
return svluti2_lane_zt_f16_x2(0, zn, 7);
121121
}
122122

@@ -138,7 +138,7 @@ svfloat16x2_t test_svluti2_lane_zt_f16(svuint8_t zn) __arm_streaming __arm_in("z
138138
// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call <vscale x 16 x bfloat> @llvm.vector.insert.nxv16bf16.nxv8bf16(<vscale x 16 x bfloat> [[TMP2]], <vscale x 8 x bfloat> [[TMP3]], i64 8)
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// CPP-CHECK-NEXT: ret <vscale x 16 x bfloat> [[TMP4]]
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//
141-
svbfloat16x2_t test_svluti2_lane_zt_bf16(svuint8_t zn) __arm_streaming __arm_in("za") {
141+
svbfloat16x2_t test_svluti2_lane_zt_bf16(svuint8_t zn) __arm_streaming __arm_in("zt0") {
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return svluti2_lane_zt_bf16_x2(0, zn, 7);
143143
}
144144

@@ -160,7 +160,7 @@ svbfloat16x2_t test_svluti2_lane_zt_bf16(svuint8_t zn) __arm_streaming __arm_in(
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// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> [[TMP2]], <vscale x 4 x i32> [[TMP3]], i64 4)
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// CPP-CHECK-NEXT: ret <vscale x 8 x i32> [[TMP4]]
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//
163-
svuint32x2_t test_svluti2_lane_zt_u32(svuint8_t zn) __arm_streaming __arm_in("za") {
163+
svuint32x2_t test_svluti2_lane_zt_u32(svuint8_t zn) __arm_streaming __arm_in("zt0") {
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return svluti2_lane_zt_u32_x2(0, zn, 7);
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}
166166

@@ -182,7 +182,7 @@ svuint32x2_t test_svluti2_lane_zt_u32(svuint8_t zn) __arm_streaming __arm_in("za
182182
// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call <vscale x 8 x i32> @llvm.vector.insert.nxv8i32.nxv4i32(<vscale x 8 x i32> [[TMP2]], <vscale x 4 x i32> [[TMP3]], i64 4)
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// CPP-CHECK-NEXT: ret <vscale x 8 x i32> [[TMP4]]
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//
185-
svint32x2_t test_svluti2_lane_zt_s32(svuint8_t zn) __arm_streaming __arm_in("za") {
185+
svint32x2_t test_svluti2_lane_zt_s32(svuint8_t zn) __arm_streaming __arm_in("zt0") {
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return svluti2_lane_zt_s32_x2(0, zn, 7);
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}
188188

@@ -204,6 +204,6 @@ svint32x2_t test_svluti2_lane_zt_s32(svuint8_t zn) __arm_streaming __arm_in("za"
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// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float> [[TMP2]], <vscale x 4 x float> [[TMP3]], i64 4)
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// CPP-CHECK-NEXT: ret <vscale x 8 x float> [[TMP4]]
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//
207-
svfloat32x2_t test_svluti2_lane_zt_f32(svuint8_t zn) __arm_streaming __arm_in("za") {
207+
svfloat32x2_t test_svluti2_lane_zt_f32(svuint8_t zn) __arm_streaming __arm_in("zt0") {
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return svluti2_lane_zt_f32_x2(0, zn, 7);
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}

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