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[RISCV] Add Sched classes for vector crypto instructions
The vector crypto instructions may have different scheduling behavior compared to VALU operations. Instead of using scheduling resources that describe VALU operations, we give these instructions their own scheduling resources. This is similar to what we did for Zb* instructions. The sifive-p670 has vector crypto, so we model behavior for these instructions in the P600SchedModel. The numbers are based off of measurements collected internally. These numbers are a bit old and new measurments show that they may not be fully accurate. It is likley that we will refine these numbers in a follow up patch(s) based on new measurments.
1 parent ebd7a58 commit 23cc0d6

16 files changed

+805
-357
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td

Lines changed: 207 additions & 65 deletions
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‎llvm/lib/Target/RISCV/RISCVSchedRocket.td

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@@ -262,4 +262,5 @@ defm : UnsupportedSchedZfa;
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defm : UnsupportedSchedZfh;
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defm : UnsupportedSchedSFB;
264264
defm : UnsupportedSchedXsfvcp;
265+
defm : UnsupportedSchedZvk;
265266
}

‎llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

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@@ -1298,4 +1298,5 @@ defm : UnsupportedSchedZbc;
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defm : UnsupportedSchedZbkb;
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defm : UnsupportedSchedZbkx;
13001300
defm : UnsupportedSchedZfa;
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defm : UnsupportedSchedZvk;
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}

‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td

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@@ -367,4 +367,5 @@ defm : UnsupportedSchedSFB;
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defm : UnsupportedSchedZfa;
368368
defm : UnsupportedSchedV;
369369
defm : UnsupportedSchedXsfvcp;
370+
defm : UnsupportedSchedZvk;
370371
}

‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td

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Original file line numberDiff line numberDiff line change
@@ -748,6 +748,63 @@ foreach mx = SchedMxList in {
748748
}
749749
}
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751+
// Vector Crypto
752+
foreach mx = SchedMxList in {
753+
defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
754+
defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
755+
// Zvbb
756+
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
757+
defm "" : LMULWriteResMX<"WriteVBREVV", [SiFiveP600VectorArith], mx, IsWorstCase>;
758+
defm "" : LMULWriteResMX<"WriteVCLZV", [SiFiveP600VectorArith], mx, IsWorstCase>;
759+
defm "" : LMULWriteResMX<"WriteVCPOPV", [SiFiveP600VectorArith], mx, IsWorstCase>;
760+
defm "" : LMULWriteResMX<"WriteVCTZV", [SiFiveP600VectorArith], mx, IsWorstCase>;
761+
defm "" : LMULWriteResMX<"WriteVWSLLV", [SiFiveP600VectorArith], mx, IsWorstCase>;
762+
}
763+
// Zvbc
764+
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
765+
defm "" : LMULWriteResMX<"WriteVCLMULV", [SiFiveP600VectorArith], mx, IsWorstCase>;
766+
defm "" : LMULWriteResMX<"WriteVCLMULX", [SiFiveP600VectorArith], mx, IsWorstCase>;
767+
}
768+
// Zvkb
769+
let Latency = 1, ReleaseAtCycles = [LMulLat] in {
770+
defm "" : LMULWriteResMX<"WriteVANDNV", [SiFiveP600VectorArith], mx, IsWorstCase>;
771+
defm "" : LMULWriteResMX<"WriteVANDNX", [SiFiveP600VectorArith], mx, IsWorstCase>;
772+
}
773+
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
774+
defm "" : LMULWriteResMX<"WriteVBREV8V", [SiFiveP600VectorArith], mx, IsWorstCase>;
775+
defm "" : LMULWriteResMX<"WriteVREV8V", [SiFiveP600VectorArith], mx, IsWorstCase>;
776+
defm "" : LMULWriteResMX<"WriteVRotV", [SiFiveP600VectorArith], mx, IsWorstCase>;
777+
defm "" : LMULWriteResMX<"WriteVRotX", [SiFiveP600VectorArith], mx, IsWorstCase>;
778+
defm "" : LMULWriteResMX<"WriteVRotI", [SiFiveP600VectorArith], mx, IsWorstCase>;
779+
}
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// Zvkg
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let Latency = 2, ReleaseAtCycles = [LMulLat] in {
782+
defm "" : LMULWriteResMX<"WriteVGHSHV", [SiFiveP600VectorArith], mx, IsWorstCase>;
783+
defm "" : LMULWriteResMX<"WriteVGMULV", [SiFiveP600VectorArith], mx, IsWorstCase>;
784+
}
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// ZvknhaOrZvknhb
786+
let Latency = 3, ReleaseAtCycles = [LMulLat] in {
787+
defm "" : LMULWriteResMX<"WriteVSHA2CHV", [SiFiveP600VectorArith], mx, IsWorstCase>;
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defm "" : LMULWriteResMX<"WriteVSHA2CLV", [SiFiveP600VectorArith], mx, IsWorstCase>;
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defm "" : LMULWriteResMX<"WriteVSHA2MSV", [SiFiveP600VectorArith], mx, IsWorstCase>;
790+
}
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// Zvkned
792+
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
793+
defm "" : LMULWriteResMX<"WriteVAESMVV", [SiFiveP600VectorArith], mx, IsWorstCase>;
794+
defm "" : LMULWriteResMX<"WriteVAESKF1V", [SiFiveP600VectorArith], mx, IsWorstCase>;
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defm "" : LMULWriteResMX<"WriteVAESKF2V", [SiFiveP600VectorArith], mx, IsWorstCase>;
796+
}
797+
let Latency = 1, ReleaseAtCycles = [LMulLat] in
798+
defm "" : LMULWriteResMX<"WriteVAESZV", [SiFiveP600VectorArith], mx, IsWorstCase>;
799+
// Zvksed
800+
let Latency = 3, ReleaseAtCycles = [LMulLat] in {
801+
defm "" : LMULWriteResMX<"WriteVSM4KV", [SiFiveP600VEXQ0], mx, IsWorstCase>;
802+
defm "" : LMULWriteResMX<"WriteVSM4RV", [SiFiveP600VEXQ0], mx, IsWorstCase>;
803+
defm "" : LMULWriteResMX<"WriteVSM3CV", [SiFiveP600VEXQ0], mx, IsWorstCase>;
804+
defm "" : LMULWriteResMX<"WriteVSM3MEV", [SiFiveP600VEXQ0], mx, IsWorstCase>;
805+
}
806+
}
807+
751808
// Others
752809
def : WriteRes<WriteCSR, [SiFiveP600SYS]>;
753810
def : WriteRes<WriteNop, []>;
@@ -1032,6 +1089,42 @@ foreach mx = SchedMxList in {
10321089
def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx # "_E" # sew), 0>;
10331090
}
10341091

1092+
// Vector Crypto Extensions
1093+
// Zvbb
1094+
defm "" : LMULReadAdvance<"ReadVBREVV", 0>;
1095+
defm "" : LMULReadAdvance<"ReadVCLZV", 0>;
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defm "" : LMULReadAdvance<"ReadVCPOPV", 0>;
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defm "" : LMULReadAdvance<"ReadVCTZV", 0>;
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defm "" : LMULReadAdvance<"ReadVWSLLV", 0>;
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// Zvbc
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defm "" : LMULReadAdvance<"ReadVCLMULV", 0>;
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defm "" : LMULReadAdvance<"ReadVCLMULX", 0>;
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// Zvkb
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defm "" : LMULReadAdvance<"ReadVANDNV", 0>;
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defm "" : LMULReadAdvance<"ReadVANDNX", 0>;
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defm "" : LMULReadAdvance<"ReadVBREV8V", 0>;
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defm "" : LMULReadAdvance<"ReadVREV8V", 0>;
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defm "" : LMULReadAdvance<"ReadVRotV", 0>;
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defm "" : LMULReadAdvance<"ReadVRotX", 0>;
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// Zvkg
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defm "" : LMULReadAdvance<"ReadVGHSHV", 0>;
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defm "" : LMULReadAdvance<"ReadVGMULV", 0>;
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// Zvknha or Zvknhb
1113+
defm "" : LMULReadAdvance<"ReadVSHA2CHV", 0>;
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defm "" : LMULReadAdvance<"ReadVSHA2CLV", 0>;
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defm "" : LMULReadAdvance<"ReadVSHA2MSV", 0>;
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// Zvkned
1117+
defm "" : LMULReadAdvance<"ReadVAESMVV", 0>;
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defm "" : LMULReadAdvance<"ReadVAESKF1V", 0>;
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defm "" : LMULReadAdvance<"ReadVAESKF2V", 0>;
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defm "" : LMULReadAdvance<"ReadVAESZV", 0>;
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// Zvksed
1122+
defm "" : LMULReadAdvance<"ReadVSM4KV", 0>;
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defm "" : LMULReadAdvance<"ReadVSM4RV", 0>;
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// Zbksh
1125+
defm "" : LMULReadAdvance<"ReadVSM3CV", 0>;
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defm "" : LMULReadAdvance<"ReadVSM3MEV", 0>;
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10351128
//===----------------------------------------------------------------------===//
10361129
// Unsupported extensions
10371130
defm : UnsupportedSchedZabha;

‎llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td

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@@ -213,4 +213,5 @@ defm : UnsupportedSchedZbkx;
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defm : UnsupportedSchedZfa;
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defm : UnsupportedSchedZfh;
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defm : UnsupportedSchedXsfvcp;
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defm : UnsupportedSchedZvk;
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}

‎llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td

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@@ -312,4 +312,5 @@ defm : UnsupportedSchedZfh;
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defm : UnsupportedSchedSFB;
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defm : UnsupportedSchedZabha;
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defm : UnsupportedSchedXsfvcp;
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defm : UnsupportedSchedZvk;
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}

‎llvm/lib/Target/RISCV/RISCVSchedule.td

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@@ -297,3 +297,4 @@ def : ReadAdvance<ReadAtomicHD, 0>;
297297
include "RISCVScheduleZb.td"
298298
include "RISCVScheduleV.td"
299299
include "RISCVScheduleXSf.td"
300+
include "RISCVScheduleZvk.td"

‎llvm/lib/Target/RISCV/RISCVScheduleZvk.td

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@@ -0,0 +1,207 @@
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//===- RISCVScheduleB.td - RISC-V Scheduling Definitions B -*- tablegen -*-===//
2+
//
3+
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
// See https://llvm.org/LICENSE.txt for license information.
5+
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
//
7+
//===----------------------------------------------------------------------===//
8+
9+
/// Define scheduler resources associated with def operands.
10+
11+
/// Zvbb extension
12+
defm "" : LMULSchedWrites<"WriteVBREVV">;
13+
defm "" : LMULSchedWrites<"WriteVCLZV">;
14+
defm "" : LMULSchedWrites<"WriteVCPOPV">;
15+
defm "" : LMULSchedWrites<"WriteVCTZV">;
16+
defm "" : LMULSchedWrites<"WriteVWSLLV">;
17+
18+
/// Zvbc extension
19+
defm "" : LMULSchedWrites<"WriteVCLMULV">;
20+
defm "" : LMULSchedWrites<"WriteVCLMULX">;
21+
22+
/// Zvkb extension
23+
defm "" : LMULSchedWrites<"WriteVANDNV">;
24+
defm "" : LMULSchedWrites<"WriteVANDNX">;
25+
defm "" : LMULSchedWrites<"WriteVBREV8V">;
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defm "" : LMULSchedWrites<"WriteVREV8V">;
27+
defm "" : LMULSchedWrites<"WriteVRotV">;
28+
defm "" : LMULSchedWrites<"WriteVRotX">;
29+
defm "" : LMULSchedWrites<"WriteVRotI">;
30+
31+
/// Zvkg extension
32+
defm "" : LMULSchedWrites<"WriteVGHSHV">;
33+
defm "" : LMULSchedWrites<"WriteVGMULV">;
34+
35+
/// Zvknha or Zvknhb extensions
36+
defm "" : LMULSchedWrites<"WriteVSHA2CHV">;
37+
defm "" : LMULSchedWrites<"WriteVSHA2CLV">;
38+
defm "" : LMULSchedWrites<"WriteVSHA2MSV">;
39+
40+
/// Zvkned extension
41+
defm "" : LMULSchedWrites<"WriteVAESMVV">;
42+
defm "" : LMULSchedWrites<"WriteVAESKF1V">;
43+
defm "" : LMULSchedWrites<"WriteVAESKF2V">;
44+
defm "" : LMULSchedWrites<"WriteVAESZV">;
45+
46+
/// Zvksed extension
47+
defm "" : LMULSchedWrites<"WriteVSM4KV">;
48+
defm "" : LMULSchedWrites<"WriteVSM4RV">;
49+
50+
/// Zvksh extension
51+
defm "" : LMULSchedWrites<"WriteVSM3CV">;
52+
defm "" : LMULSchedWrites<"WriteVSM3MEV">;
53+
54+
/// Define scheduler resources associated with use operands.
55+
/// Zvbb extension
56+
defm "" : LMULSchedReads<"ReadVBREVV">;
57+
defm "" : LMULSchedReads<"ReadVCLZV">;
58+
defm "" : LMULSchedReads<"ReadVCPOPV">;
59+
defm "" : LMULSchedReads<"ReadVCTZV">;
60+
defm "" : LMULSchedReads<"ReadVWSLLV">;
61+
62+
/// Zvbc extension
63+
defm "" : LMULSchedReads<"ReadVCLMULV">;
64+
defm "" : LMULSchedReads<"ReadVCLMULX">;
65+
66+
/// Zvkb extension
67+
defm "" : LMULSchedReads<"ReadVANDNV">;
68+
defm "" : LMULSchedReads<"ReadVANDNX">;
69+
defm "" : LMULSchedReads<"ReadVBREV8V">;
70+
defm "" : LMULSchedReads<"ReadVREV8V">;
71+
defm "" : LMULSchedReads<"ReadVRotV">;
72+
defm "" : LMULSchedReads<"ReadVRotX">;
73+
74+
/// Zvkg extension
75+
defm "" : LMULSchedReads<"ReadVGHSHV">;
76+
defm "" : LMULSchedReads<"ReadVGMULV">;
77+
78+
/// Zvknha or Zvknhb extensions
79+
defm "" : LMULSchedReads<"ReadVSHA2CHV">;
80+
defm "" : LMULSchedReads<"ReadVSHA2CLV">;
81+
defm "" : LMULSchedReads<"ReadVSHA2MSV">;
82+
83+
/// Zvkned extension
84+
defm "" : LMULSchedReads<"ReadVAESMVV">;
85+
defm "" : LMULSchedReads<"ReadVAESKF1V">;
86+
defm "" : LMULSchedReads<"ReadVAESKF2V">;
87+
defm "" : LMULSchedReads<"ReadVAESZV">;
88+
89+
/// Zvksed extension
90+
defm "" : LMULSchedReads<"ReadVSM4KV">;
91+
defm "" : LMULSchedReads<"ReadVSM4RV">;
92+
93+
/// Zvksh extension
94+
defm "" : LMULSchedReads<"ReadVSM3CV">;
95+
defm "" : LMULSchedReads<"ReadVSM3MEV">;
96+
97+
multiclass UnsupportedSchedZvbb {
98+
let Unsupported = true in {
99+
defm "" : LMULWriteRes<"WriteVBREVV", []>;
100+
defm "" : LMULWriteRes<"WriteVCLZV", []>;
101+
defm "" : LMULWriteRes<"WriteVCPOPV", []>;
102+
defm "" : LMULWriteRes<"WriteVCTZV", []>;
103+
defm "" : LMULWriteRes<"WriteVWSLLV", []>;
104+
105+
defm "" : LMULReadAdvance<"ReadVBREVV", 0>;
106+
defm "" : LMULReadAdvance<"ReadVCLZV", 0>;
107+
defm "" : LMULReadAdvance<"ReadVCPOPV", 0>;
108+
defm "" : LMULReadAdvance<"ReadVCTZV", 0>;
109+
defm "" : LMULReadAdvance<"ReadVWSLLV", 0>;
110+
}
111+
}
112+
113+
multiclass UnsupportedSchedZvbc {
114+
let Unsupported = true in {
115+
defm "" : LMULWriteRes<"WriteVCLMULV", []>;
116+
defm "" : LMULWriteRes<"WriteVCLMULX", []>;
117+
118+
defm "" : LMULReadAdvance<"ReadVCLMULV", 0>;
119+
defm "" : LMULReadAdvance<"ReadVCLMULX", 0>;
120+
}
121+
}
122+
123+
multiclass UnsupportedSchedZvkb {
124+
let Unsupported = true in {
125+
defm "" : LMULWriteRes<"WriteVANDNV", []>;
126+
defm "" : LMULWriteRes<"WriteVANDNX", []>;
127+
defm "" : LMULWriteRes<"WriteVBREV8V", []>;
128+
defm "" : LMULWriteRes<"WriteVREV8V", []>;
129+
defm "" : LMULWriteRes<"WriteVRotV", []>;
130+
defm "" : LMULWriteRes<"WriteVRotX", []>;
131+
defm "" : LMULWriteRes<"WriteVRotI", []>;
132+
133+
defm "" : LMULReadAdvance<"ReadVANDNV", 0>;
134+
defm "" : LMULReadAdvance<"ReadVBREV8V", 0>;
135+
defm "" : LMULReadAdvance<"ReadVREV8V", 0>;
136+
defm "" : LMULReadAdvance<"ReadVRotV", 0>;
137+
defm "" : LMULReadAdvance<"ReadVRotX", 0>;
138+
}
139+
}
140+
141+
multiclass UnsupportedSchedZvkg {
142+
let Unsupported = true in {
143+
defm "" : LMULWriteRes<"WriteVGHSHV", []>;
144+
defm "" : LMULWriteRes<"WriteVGMULV", []>;
145+
146+
defm "" : LMULReadAdvance<"ReadVGHSHV", 0>;
147+
defm "" : LMULReadAdvance<"ReadVGMULV", 0>;
148+
}
149+
}
150+
151+
multiclass UnsupportedSchedZvknhaOrZvknhb {
152+
let Unsupported = true in {
153+
defm "" : LMULWriteRes<"WriteVSHA2CHV", []>;
154+
defm "" : LMULWriteRes<"WriteVSHA2CLV", []>;
155+
defm "" : LMULWriteRes<"WriteVSHA2MSV", []>;
156+
157+
defm "" : LMULReadAdvance<"ReadVSHA2CHV", 0>;
158+
defm "" : LMULReadAdvance<"ReadVSHA2CLV", 0>;
159+
defm "" : LMULReadAdvance<"ReadVSHA2MSV", 0>;
160+
}
161+
}
162+
163+
multiclass UnsupportedSchedZvkned {
164+
let Unsupported = true in {
165+
defm "" : LMULWriteRes<"WriteVAESMVV", []>;
166+
defm "" : LMULWriteRes<"WriteVAESKF1V", []>;
167+
defm "" : LMULWriteRes<"WriteVAESKF2V", []>;
168+
defm "" : LMULWriteRes<"WriteVAESZV", []>;
169+
170+
defm "" : LMULReadAdvance<"ReadVAESMVV", 0>;
171+
defm "" : LMULReadAdvance<"ReadVAESKF1V", 0>;
172+
defm "" : LMULReadAdvance<"ReadVAESKF2V", 0>;
173+
defm "" : LMULReadAdvance<"ReadVAESZV", 0>;
174+
}
175+
}
176+
177+
multiclass UnsupportedSchedZvksed {
178+
let Unsupported = true in {
179+
defm "" : LMULWriteRes<"WriteVSM4KV", []>;
180+
defm "" : LMULWriteRes<"WriteVSM4RV", []>;
181+
182+
defm "" : LMULReadAdvance<"ReadVSM4KV", 0>;
183+
defm "" : LMULReadAdvance<"ReadVSM4RV", 0>;
184+
}
185+
}
186+
187+
multiclass UnsupportedSchedZvksh {
188+
let Unsupported = true in {
189+
defm "" : LMULWriteRes<"WriteVSM3CV", []>;
190+
defm "" : LMULWriteRes<"WriteVSM3MEV", []>;
191+
192+
defm "" : LMULReadAdvance<"ReadVSM3CV", 0>;
193+
defm "" : LMULReadAdvance<"ReadVSM3MEV", 0>;
194+
}
195+
}
196+
197+
// Helper class to define all RISC-V Vector Crypto extensions as unsupported
198+
multiclass UnsupportedSchedZvk {
199+
defm "" : UnsupportedSchedZvbb;
200+
defm "" : UnsupportedSchedZvbc;
201+
defm "" : UnsupportedSchedZvkb;
202+
defm "" : UnsupportedSchedZvkg;
203+
defm "" : UnsupportedSchedZvknhaOrZvknhb;
204+
defm "" : UnsupportedSchedZvkned;
205+
defm "" : UnsupportedSchedZvksed;
206+
defm "" : UnsupportedSchedZvksh;
207+
}

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