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‎llvm/test/CodeGen/RISCV/pr101786.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc --mtriple=riscv64 -o - %s | FileCheck %s
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define i64 @test(i64 %x, ptr %p) {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mv a2, a0
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; CHECK-NEXT: li a0, 0
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; CHECK-NEXT: bgtz a2, .LBB0_3
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; CHECK-NEXT: # %bb.1: # %entry
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; CHECK-NEXT: srli a3, a2, 1
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; CHECK-NEXT: lui a4, 349525
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; CHECK-NEXT: addiw a4, a4, 1365
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; CHECK-NEXT: slli a5, a4, 32
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; CHECK-NEXT: add a4, a4, a5
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; CHECK-NEXT: and a3, a3, a4
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; CHECK-NEXT: sub a2, a2, a3
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; CHECK-NEXT: lui a3, 209715
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; CHECK-NEXT: addiw a3, a3, 819
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; CHECK-NEXT: slli a4, a3, 32
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; CHECK-NEXT: add a3, a3, a4
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; CHECK-NEXT: and a4, a2, a3
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; CHECK-NEXT: srli a2, a2, 2
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; CHECK-NEXT: and a2, a2, a3
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; CHECK-NEXT: add a2, a4, a2
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; CHECK-NEXT: srli a3, a2, 4
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; CHECK-NEXT: add a2, a2, a3
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; CHECK-NEXT: lui a3, 61681
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; CHECK-NEXT: addiw a3, a3, -241
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; CHECK-NEXT: slli a4, a3, 32
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; CHECK-NEXT: add a3, a3, a4
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; CHECK-NEXT: and a2, a2, a3
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; CHECK-NEXT: slli a3, a2, 8
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; CHECK-NEXT: add a2, a2, a3
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; CHECK-NEXT: slli a3, a2, 16
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; CHECK-NEXT: add a2, a2, a3
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; CHECK-NEXT: slli a3, a2, 32
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; CHECK-NEXT: add a2, a2, a3
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; CHECK-NEXT: srli a2, a2, 56
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; CHECK-NEXT: li a3, 1
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; CHECK-NEXT: bltu a3, a2, .LBB0_3
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; CHECK-NEXT: # %bb.2: # %if.else
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; CHECK-NEXT: ld a0, 0(a1)
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; CHECK-NEXT: .LBB0_3: # %if.end
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; CHECK-NEXT: ret
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entry:
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%ctpop = call i64 @llvm.ctpop.i64(i64 %x)
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%cmp1 = icmp ugt i64 %ctpop, 1
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%cmp2 = icmp sgt i64 %x, 0
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%or = or i1 %cmp2, %cmp1
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br i1 %or, label %if.end, label %if.else
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if.else:
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%load = load i64, ptr %p, align 8
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br label %if.end
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if.end:
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%res = phi i64 [0, %entry], [%load, %if.else]
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ret i64 %res
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}

‎llvm/test/CodeGen/X86/pr94829.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc --mtriple=x86_64 -o - %s | FileCheck %s
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define ptr @test(i64 %x) {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: shrq %rax
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; CHECK-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555
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; CHECK-NEXT: andq %rax, %rcx
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; CHECK-NEXT: subq %rcx, %rdi
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; CHECK-NEXT: movabsq $3689348814741910323, %rax # imm = 0x3333333333333333
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; CHECK-NEXT: movq %rdi, %rcx
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; CHECK-NEXT: andq %rax, %rcx
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; CHECK-NEXT: shrq $2, %rdi
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; CHECK-NEXT: andq %rax, %rdi
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; CHECK-NEXT: addq %rcx, %rdi
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: shrq $4, %rax
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; CHECK-NEXT: addq %rdi, %rax
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; CHECK-NEXT: movabsq $1085102592571150095, %rcx # imm = 0xF0F0F0F0F0F0F0F
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; CHECK-NEXT: andq %rax, %rcx
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; CHECK-NEXT: movabsq $72340172838076673, %rax # imm = 0x101010101010101
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; CHECK-NEXT: imulq %rcx, %rax
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; CHECK-NEXT: shrq $56, %rax
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; CHECK-NEXT: cmpq $2, %rax
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; CHECK-NEXT: jb .LBB0_2
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; CHECK-NEXT: # %bb.1: # %if.else
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; CHECK-NEXT: cmpl $2, %eax
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; CHECK-NEXT: .LBB0_2: # %exit1
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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entry:
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%ctpop = tail call i64 @llvm.ctpop.i64(i64 %x)
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%cmp = icmp ult i64 %ctpop, 2
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br i1 %cmp, label %exit1, label %if.else
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if.else:
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br i1 %cmp, label %exit2, label %exit3
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exit1:
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ret ptr null
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exit2:
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ret ptr null
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exit3:
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ret ptr null
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}

‎llvm/test/Transforms/CodeGenPrepare/unfold-pow2-test.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -p 'require<profile-summary>,function(codegenprepare)' -S %s \
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; RUN: | FileCheck %s --check-prefix=SLOW
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; RUN: opt -p 'require<profile-summary>,function(codegenprepare)' -S --mattr=+zbb %s \
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; RUN: | FileCheck %s --check-prefix=FAST
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; REQUIRES: riscv64-registered-target
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target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
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target triple = "riscv64"
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define i64 @test_ult_2(i64 %x, i64 %y, i64 %a, i64 %b) {
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; SLOW-LABEL: define i64 @test_ult_2(
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; SLOW-SAME: i64 [[X:%.*]], i64 [[Y:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) {
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; SLOW-NEXT: [[ENTRY:.*]]:
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; SLOW-NEXT: [[CTPOP:%.*]] = call i64 @llvm.ctpop.i64(i64 [[X]])
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; SLOW-NEXT: [[CMP1:%.*]] = icmp ugt i64 [[CTPOP]], 1
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; SLOW-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[Y]], 0
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; SLOW-NEXT: [[CMP:%.*]] = or i1 [[CMP2]], [[CMP1]]
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; SLOW-NEXT: br i1 [[CMP]], label %[[IF_THEN:.*]], label %[[IF_END:.*]]
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; SLOW: [[IF_THEN]]:
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; SLOW-NEXT: br label %[[IF_END]]
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; SLOW: [[IF_END]]:
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; SLOW-NEXT: [[RES:%.*]] = phi i64 [ [[A]], %[[IF_THEN]] ], [ [[B]], %[[ENTRY]] ]
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; SLOW-NEXT: ret i64 [[RES]]
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;
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; FAST-LABEL: define i64 @test_ult_2(
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; FAST-SAME: i64 [[X:%.*]], i64 [[Y:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0:[0-9]+]] {
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; FAST-NEXT: [[ENTRY:.*]]:
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; FAST-NEXT: [[CTPOP:%.*]] = call i64 @llvm.ctpop.i64(i64 [[X]])
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; FAST-NEXT: [[CMP1:%.*]] = icmp ugt i64 [[CTPOP]], 1
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; FAST-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[Y]], 0
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; FAST-NEXT: [[CMP:%.*]] = or i1 [[CMP2]], [[CMP1]]
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; FAST-NEXT: br i1 [[CMP]], label %[[IF_THEN:.*]], label %[[IF_END:.*]]
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; FAST: [[IF_THEN]]:
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; FAST-NEXT: br label %[[IF_END]]
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; FAST: [[IF_END]]:
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; FAST-NEXT: [[RES:%.*]] = phi i64 [ [[A]], %[[IF_THEN]] ], [ [[B]], %[[ENTRY]] ]
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; FAST-NEXT: ret i64 [[RES]]
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;
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entry:
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%ctpop = call i64 @llvm.ctpop.i64(i64 %x)
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%cmp1 = icmp ugt i64 %ctpop, 1
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%cmp2 = icmp sgt i64 %y, 0
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%cmp = or i1 %cmp2, %cmp1
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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br label %if.end
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if.end:
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%res = phi i64 [ %a, %if.then ], [ %b, %entry ]
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ret i64 %res
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}
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define i64 @test_ugt_1(i64 %x, i64 %y, i64 %a, i64 %b) {
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; SLOW-LABEL: define i64 @test_ugt_1(
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; SLOW-SAME: i64 [[X:%.*]], i64 [[Y:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) {
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; SLOW-NEXT: [[ENTRY:.*]]:
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; SLOW-NEXT: [[CTPOP:%.*]] = call i64 @llvm.ctpop.i64(i64 [[X]])
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; SLOW-NEXT: [[CMP1:%.*]] = icmp ugt i64 [[CTPOP]], 1
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; SLOW-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[Y]], 0
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; SLOW-NEXT: [[CMP:%.*]] = or i1 [[CMP2]], [[CMP1]]
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; SLOW-NEXT: br i1 [[CMP]], label %[[IF_THEN:.*]], label %[[IF_END:.*]]
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; SLOW: [[IF_THEN]]:
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; SLOW-NEXT: br label %[[IF_END]]
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; SLOW: [[IF_END]]:
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; SLOW-NEXT: [[RES:%.*]] = phi i64 [ [[A]], %[[IF_THEN]] ], [ [[B]], %[[ENTRY]] ]
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; SLOW-NEXT: ret i64 [[RES]]
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;
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; FAST-LABEL: define i64 @test_ugt_1(
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; FAST-SAME: i64 [[X:%.*]], i64 [[Y:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
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; FAST-NEXT: [[ENTRY:.*]]:
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; FAST-NEXT: [[CTPOP:%.*]] = call i64 @llvm.ctpop.i64(i64 [[X]])
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; FAST-NEXT: [[CMP1:%.*]] = icmp ugt i64 [[CTPOP]], 1
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; FAST-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[Y]], 0
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; FAST-NEXT: [[CMP:%.*]] = or i1 [[CMP2]], [[CMP1]]
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; FAST-NEXT: br i1 [[CMP]], label %[[IF_THEN:.*]], label %[[IF_END:.*]]
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; FAST: [[IF_THEN]]:
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; FAST-NEXT: br label %[[IF_END]]
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; FAST: [[IF_END]]:
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; FAST-NEXT: [[RES:%.*]] = phi i64 [ [[A]], %[[IF_THEN]] ], [ [[B]], %[[ENTRY]] ]
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; FAST-NEXT: ret i64 [[RES]]
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;
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entry:
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%ctpop = call i64 @llvm.ctpop.i64(i64 %x)
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%cmp1 = icmp ugt i64 %ctpop, 1
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%cmp2 = icmp sgt i64 %y, 0
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%cmp = or i1 %cmp2, %cmp1
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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br label %if.end
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if.end:
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%res = phi i64 [ %a, %if.then ], [ %b, %entry ]
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ret i64 %res
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}

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