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[RISCV] Add patterns for vnsr[a,l].wx where shift amount has different type than vector element
We're currently only matching scalar shift amounts where the type is the same as the vector element type. But because only the bottom log2(2*SEW) bits are used, only 7 bits will be used at most so we can use any scalar type >= i8. This patch adds patterns for the case above, as well as for when the shift amount type is the same as the widened element type and doesn't need extended. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D155698
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8 files changed

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‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3016,6 +3016,16 @@ bool RISCVDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &SplatVal) {
30163016
return true;
30173017
}
30183018

3019+
bool RISCVDAGToDAGISel::selectExtOneUseVSplat(SDValue N, SDValue &SplatVal) {
3020+
if (N->getOpcode() == ISD::SIGN_EXTEND ||
3021+
N->getOpcode() == ISD::ZERO_EXTEND) {
3022+
if (!N.hasOneUse())
3023+
return false;
3024+
N = N->getOperand(0);
3025+
}
3026+
return selectVSplat(N, SplatVal);
3027+
}
3028+
30193029
bool RISCVDAGToDAGISel::selectFPImm(SDValue N, SDValue &Imm) {
30203030
ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N.getNode());
30213031
if (!CFP)

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -131,6 +131,7 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
131131
bool selectVSplatUimm5(SDValue N, SDValue &SplatVal);
132132
bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal);
133133
bool selectVSplatSimm5Plus1NonZero(SDValue N, SDValue &SplatVal);
134+
bool selectExtOneUseVSplat(SDValue N, SDValue &SplatVal);
134135
bool selectFPImm(SDValue N, SDValue &Imm);
135136

136137
bool selectRVVSimm5(SDValue N, unsigned Width, SDValue &Imm);

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1234,6 +1234,8 @@ def zexti32 : ComplexPattern<i64, 1, "selectZExtBits<32>">;
12341234
def zexti16 : ComplexPattern<XLenVT, 1, "selectZExtBits<16>">;
12351235
def zexti8 : ComplexPattern<XLenVT, 1, "selectZExtBits<8>">;
12361236

1237+
def ext : PatFrags<(ops node:$A), [(sext node:$A), (zext node:$A)]>;
1238+
12371239
class binop_oneuse<SDPatternOperator operator>
12381240
: PatFrag<(ops node:$A, node:$B),
12391241
(operator node:$A, node:$B), [{
@@ -1259,6 +1261,7 @@ class unop_oneuse<SDPatternOperator operator>
12591261
def sext_oneuse : unop_oneuse<sext>;
12601262
def zext_oneuse : unop_oneuse<zext>;
12611263
def anyext_oneuse : unop_oneuse<anyext>;
1264+
def ext_oneuse : unop_oneuse<ext>;
12621265
def fpext_oneuse : unop_oneuse<any_fpextend>;
12631266

12641267
/// Simple arithmetic operations

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Lines changed: 12 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -569,12 +569,15 @@ foreach kind = ["ADD", "UMAX", "SMAX", "UMIN", "SMIN", "AND", "OR", "XOR",
569569

570570
// Give explicit Complexity to prefer simm5/uimm5.
571571
def SplatPat : ComplexPattern<vAny, 1, "selectVSplat", [], [], 1>;
572-
def SplatPat_simm5 : ComplexPattern<vAny, 1, "selectVSplatSimm5", [], [], 2>;
573-
def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", [], [], 2>;
572+
def SplatPat_simm5 : ComplexPattern<vAny, 1, "selectVSplatSimm5", [], [], 3>;
573+
def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", [], [], 3>;
574574
def SplatPat_simm5_plus1
575-
: ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1", [], [], 2>;
575+
: ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1", [], [], 3>;
576576
def SplatPat_simm5_plus1_nonzero
577-
: ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1NonZero", [], [], 2>;
577+
: ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1NonZero", [], [], 3>;
578+
579+
def ext_oneuse_SplatPat
580+
: ComplexPattern<vAny, 1, "selectExtOneUseVSplat", [], [], 2>;
578581

579582
def SelectFPImm : ComplexPattern<fAny, 1, "selectFPImm", [], [], 1>;
580583

@@ -1428,7 +1431,7 @@ multiclass VPatReductionVL_RM<SDNode vop, string instruction_name, bit is_float>
14281431
}
14291432
}
14301433

1431-
multiclass VPatBinaryExtVL_WV_WX<SDNode op, PatFrags extop, string instruction_name> {
1434+
multiclass VPatBinaryExtVL_WV_WX<SDNode op, string instruction_name> {
14321435
foreach vtiToWti = AllWidenableIntVectors in {
14331436
defvar vti = vtiToWti.Vti;
14341437
defvar wti = vtiToWti.Wti;
@@ -1438,17 +1441,18 @@ multiclass VPatBinaryExtVL_WV_WX<SDNode op, PatFrags extop, string instruction_n
14381441
(vti.Vector
14391442
(riscv_trunc_vector_vl
14401443
(op (wti.Vector wti.RegClass:$rs2),
1441-
(wti.Vector (extop (vti.Vector vti.RegClass:$rs1)))),
1444+
(wti.Vector (ext_oneuse (vti.Vector vti.RegClass:$rs1)))),
14421445
(vti.Mask true_mask),
14431446
VLOpFrag)),
14441447
(!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX)
14451448
(vti.Vector (IMPLICIT_DEF)),
14461449
wti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW, TU_MU)>;
1450+
14471451
def : Pat<
14481452
(vti.Vector
14491453
(riscv_trunc_vector_vl
14501454
(op (wti.Vector wti.RegClass:$rs2),
1451-
(wti.Vector (extop (vti.Vector (SplatPat (XLenVT GPR:$rs1)))))),
1455+
(wti.Vector (ext_oneuse_SplatPat (XLenVT GPR:$rs1)))),
14521456
(vti.Mask true_mask),
14531457
VLOpFrag)),
14541458
(!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX)
@@ -1459,8 +1463,7 @@ multiclass VPatBinaryExtVL_WV_WX<SDNode op, PatFrags extop, string instruction_n
14591463
}
14601464

14611465
multiclass VPatBinaryVL_WV_WX_WI<SDNode op, string instruction_name>
1462-
: VPatBinaryExtVL_WV_WX<op, sext_oneuse, instruction_name>,
1463-
VPatBinaryExtVL_WV_WX<op, zext_oneuse, instruction_name> {
1466+
: VPatBinaryExtVL_WV_WX<op, instruction_name> {
14641467
foreach vtiToWti = AllWidenableIntVectors in {
14651468
defvar vti = vtiToWti.Vti;
14661469
defvar wti = vtiToWti.Wti;

‎llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll

Lines changed: 14 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -1056,10 +1056,7 @@ define <vscale x 1 x i32> @ctlz_nxv1i32(<vscale x 1 x i32> %va) {
10561056
; CHECK-D-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
10571057
; CHECK-D-NEXT: vfwcvt.f.xu.v v9, v8
10581058
; CHECK-D-NEXT: li a0, 52
1059-
; CHECK-D-NEXT: vsetvli zero, zero, e64, m1, ta, ma
1060-
; CHECK-D-NEXT: vsrl.vx v8, v9, a0
1061-
; CHECK-D-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
1062-
; CHECK-D-NEXT: vnsrl.wi v8, v8, 0
1059+
; CHECK-D-NEXT: vnsrl.wx v8, v9, a0
10631060
; CHECK-D-NEXT: li a0, 1054
10641061
; CHECK-D-NEXT: vrsub.vx v8, v8, a0
10651062
; CHECK-D-NEXT: li a0, 32
@@ -1167,12 +1164,9 @@ define <vscale x 2 x i32> @ctlz_nxv2i32(<vscale x 2 x i32> %va) {
11671164
; CHECK-D-NEXT: vsetvli a0, zero, e32, m1, ta, ma
11681165
; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v8
11691166
; CHECK-D-NEXT: li a0, 52
1170-
; CHECK-D-NEXT: vsetvli zero, zero, e64, m2, ta, ma
1171-
; CHECK-D-NEXT: vsrl.vx v8, v10, a0
1172-
; CHECK-D-NEXT: vsetvli zero, zero, e32, m1, ta, ma
1173-
; CHECK-D-NEXT: vnsrl.wi v10, v8, 0
1167+
; CHECK-D-NEXT: vnsrl.wx v8, v10, a0
11741168
; CHECK-D-NEXT: li a0, 1054
1175-
; CHECK-D-NEXT: vrsub.vx v8, v10, a0
1169+
; CHECK-D-NEXT: vrsub.vx v8, v8, a0
11761170
; CHECK-D-NEXT: li a0, 32
11771171
; CHECK-D-NEXT: vminu.vx v8, v8, a0
11781172
; CHECK-D-NEXT: ret
@@ -1278,12 +1272,9 @@ define <vscale x 4 x i32> @ctlz_nxv4i32(<vscale x 4 x i32> %va) {
12781272
; CHECK-D-NEXT: vsetvli a0, zero, e32, m2, ta, ma
12791273
; CHECK-D-NEXT: vfwcvt.f.xu.v v12, v8
12801274
; CHECK-D-NEXT: li a0, 52
1281-
; CHECK-D-NEXT: vsetvli zero, zero, e64, m4, ta, ma
1282-
; CHECK-D-NEXT: vsrl.vx v8, v12, a0
1283-
; CHECK-D-NEXT: vsetvli zero, zero, e32, m2, ta, ma
1284-
; CHECK-D-NEXT: vnsrl.wi v12, v8, 0
1275+
; CHECK-D-NEXT: vnsrl.wx v8, v12, a0
12851276
; CHECK-D-NEXT: li a0, 1054
1286-
; CHECK-D-NEXT: vrsub.vx v8, v12, a0
1277+
; CHECK-D-NEXT: vrsub.vx v8, v8, a0
12871278
; CHECK-D-NEXT: li a0, 32
12881279
; CHECK-D-NEXT: vminu.vx v8, v8, a0
12891280
; CHECK-D-NEXT: ret
@@ -1389,12 +1380,9 @@ define <vscale x 8 x i32> @ctlz_nxv8i32(<vscale x 8 x i32> %va) {
13891380
; CHECK-D-NEXT: vsetvli a0, zero, e32, m4, ta, ma
13901381
; CHECK-D-NEXT: vfwcvt.f.xu.v v16, v8
13911382
; CHECK-D-NEXT: li a0, 52
1392-
; CHECK-D-NEXT: vsetvli zero, zero, e64, m8, ta, ma
1393-
; CHECK-D-NEXT: vsrl.vx v8, v16, a0
1394-
; CHECK-D-NEXT: vsetvli zero, zero, e32, m4, ta, ma
1395-
; CHECK-D-NEXT: vnsrl.wi v16, v8, 0
1383+
; CHECK-D-NEXT: vnsrl.wx v8, v16, a0
13961384
; CHECK-D-NEXT: li a0, 1054
1397-
; CHECK-D-NEXT: vrsub.vx v8, v16, a0
1385+
; CHECK-D-NEXT: vrsub.vx v8, v8, a0
13981386
; CHECK-D-NEXT: li a0, 32
13991387
; CHECK-D-NEXT: vminu.vx v8, v8, a0
14001388
; CHECK-D-NEXT: ret
@@ -3099,10 +3087,7 @@ define <vscale x 1 x i32> @ctlz_zero_undef_nxv1i32(<vscale x 1 x i32> %va) {
30993087
; CHECK-D-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
31003088
; CHECK-D-NEXT: vfwcvt.f.xu.v v9, v8
31013089
; CHECK-D-NEXT: li a0, 52
3102-
; CHECK-D-NEXT: vsetvli zero, zero, e64, m1, ta, ma
3103-
; CHECK-D-NEXT: vsrl.vx v8, v9, a0
3104-
; CHECK-D-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
3105-
; CHECK-D-NEXT: vnsrl.wi v8, v8, 0
3090+
; CHECK-D-NEXT: vnsrl.wx v8, v9, a0
31063091
; CHECK-D-NEXT: li a0, 1054
31073092
; CHECK-D-NEXT: vrsub.vx v8, v8, a0
31083093
; CHECK-D-NEXT: ret
@@ -3205,12 +3190,9 @@ define <vscale x 2 x i32> @ctlz_zero_undef_nxv2i32(<vscale x 2 x i32> %va) {
32053190
; CHECK-D-NEXT: vsetvli a0, zero, e32, m1, ta, ma
32063191
; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v8
32073192
; CHECK-D-NEXT: li a0, 52
3208-
; CHECK-D-NEXT: vsetvli zero, zero, e64, m2, ta, ma
3209-
; CHECK-D-NEXT: vsrl.vx v8, v10, a0
3210-
; CHECK-D-NEXT: vsetvli zero, zero, e32, m1, ta, ma
3211-
; CHECK-D-NEXT: vnsrl.wi v10, v8, 0
3193+
; CHECK-D-NEXT: vnsrl.wx v8, v10, a0
32123194
; CHECK-D-NEXT: li a0, 1054
3213-
; CHECK-D-NEXT: vrsub.vx v8, v10, a0
3195+
; CHECK-D-NEXT: vrsub.vx v8, v8, a0
32143196
; CHECK-D-NEXT: ret
32153197
;
32163198
; CHECK-ZVBB-LABEL: ctlz_zero_undef_nxv2i32:
@@ -3311,12 +3293,9 @@ define <vscale x 4 x i32> @ctlz_zero_undef_nxv4i32(<vscale x 4 x i32> %va) {
33113293
; CHECK-D-NEXT: vsetvli a0, zero, e32, m2, ta, ma
33123294
; CHECK-D-NEXT: vfwcvt.f.xu.v v12, v8
33133295
; CHECK-D-NEXT: li a0, 52
3314-
; CHECK-D-NEXT: vsetvli zero, zero, e64, m4, ta, ma
3315-
; CHECK-D-NEXT: vsrl.vx v8, v12, a0
3316-
; CHECK-D-NEXT: vsetvli zero, zero, e32, m2, ta, ma
3317-
; CHECK-D-NEXT: vnsrl.wi v12, v8, 0
3296+
; CHECK-D-NEXT: vnsrl.wx v8, v12, a0
33183297
; CHECK-D-NEXT: li a0, 1054
3319-
; CHECK-D-NEXT: vrsub.vx v8, v12, a0
3298+
; CHECK-D-NEXT: vrsub.vx v8, v8, a0
33203299
; CHECK-D-NEXT: ret
33213300
;
33223301
; CHECK-ZVBB-LABEL: ctlz_zero_undef_nxv4i32:
@@ -3417,12 +3396,9 @@ define <vscale x 8 x i32> @ctlz_zero_undef_nxv8i32(<vscale x 8 x i32> %va) {
34173396
; CHECK-D-NEXT: vsetvli a0, zero, e32, m4, ta, ma
34183397
; CHECK-D-NEXT: vfwcvt.f.xu.v v16, v8
34193398
; CHECK-D-NEXT: li a0, 52
3420-
; CHECK-D-NEXT: vsetvli zero, zero, e64, m8, ta, ma
3421-
; CHECK-D-NEXT: vsrl.vx v8, v16, a0
3422-
; CHECK-D-NEXT: vsetvli zero, zero, e32, m4, ta, ma
3423-
; CHECK-D-NEXT: vnsrl.wi v16, v8, 0
3399+
; CHECK-D-NEXT: vnsrl.wx v8, v16, a0
34243400
; CHECK-D-NEXT: li a0, 1054
3425-
; CHECK-D-NEXT: vrsub.vx v8, v16, a0
3401+
; CHECK-D-NEXT: vrsub.vx v8, v8, a0
34263402
; CHECK-D-NEXT: ret
34273403
;
34283404
; CHECK-ZVBB-LABEL: ctlz_zero_undef_nxv8i32:

‎llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll

Lines changed: 11 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -1026,10 +1026,7 @@ define <vscale x 1 x i32> @cttz_nxv1i32(<vscale x 1 x i32> %va) {
10261026
; CHECK-D-NEXT: vand.vv v9, v8, v9
10271027
; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v9
10281028
; CHECK-D-NEXT: li a0, 52
1029-
; CHECK-D-NEXT: vsetvli zero, zero, e64, m1, ta, ma
1030-
; CHECK-D-NEXT: vsrl.vx v9, v10, a0
1031-
; CHECK-D-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
1032-
; CHECK-D-NEXT: vnsrl.wi v9, v9, 0
1029+
; CHECK-D-NEXT: vnsrl.wx v9, v10, a0
10331030
; CHECK-D-NEXT: li a0, 1023
10341031
; CHECK-D-NEXT: vsub.vx v9, v9, a0
10351032
; CHECK-D-NEXT: vmseq.vi v0, v8, 0
@@ -1129,10 +1126,7 @@ define <vscale x 2 x i32> @cttz_nxv2i32(<vscale x 2 x i32> %va) {
11291126
; CHECK-D-NEXT: vand.vv v9, v8, v9
11301127
; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v9
11311128
; CHECK-D-NEXT: li a0, 52
1132-
; CHECK-D-NEXT: vsetvli zero, zero, e64, m2, ta, ma
1133-
; CHECK-D-NEXT: vsrl.vx v10, v10, a0
1134-
; CHECK-D-NEXT: vsetvli zero, zero, e32, m1, ta, ma
1135-
; CHECK-D-NEXT: vnsrl.wi v9, v10, 0
1129+
; CHECK-D-NEXT: vnsrl.wx v9, v10, a0
11361130
; CHECK-D-NEXT: li a0, 1023
11371131
; CHECK-D-NEXT: vsub.vx v9, v9, a0
11381132
; CHECK-D-NEXT: vmseq.vi v0, v8, 0
@@ -1232,10 +1226,7 @@ define <vscale x 4 x i32> @cttz_nxv4i32(<vscale x 4 x i32> %va) {
12321226
; CHECK-D-NEXT: vand.vv v10, v8, v10
12331227
; CHECK-D-NEXT: vfwcvt.f.xu.v v12, v10
12341228
; CHECK-D-NEXT: li a0, 52
1235-
; CHECK-D-NEXT: vsetvli zero, zero, e64, m4, ta, ma
1236-
; CHECK-D-NEXT: vsrl.vx v12, v12, a0
1237-
; CHECK-D-NEXT: vsetvli zero, zero, e32, m2, ta, ma
1238-
; CHECK-D-NEXT: vnsrl.wi v10, v12, 0
1229+
; CHECK-D-NEXT: vnsrl.wx v10, v12, a0
12391230
; CHECK-D-NEXT: li a0, 1023
12401231
; CHECK-D-NEXT: vsub.vx v10, v10, a0
12411232
; CHECK-D-NEXT: vmseq.vi v0, v8, 0
@@ -1335,10 +1326,7 @@ define <vscale x 8 x i32> @cttz_nxv8i32(<vscale x 8 x i32> %va) {
13351326
; CHECK-D-NEXT: vand.vv v12, v8, v12
13361327
; CHECK-D-NEXT: vfwcvt.f.xu.v v16, v12
13371328
; CHECK-D-NEXT: li a0, 52
1338-
; CHECK-D-NEXT: vsetvli zero, zero, e64, m8, ta, ma
1339-
; CHECK-D-NEXT: vsrl.vx v16, v16, a0
1340-
; CHECK-D-NEXT: vsetvli zero, zero, e32, m4, ta, ma
1341-
; CHECK-D-NEXT: vnsrl.wi v12, v16, 0
1329+
; CHECK-D-NEXT: vnsrl.wx v12, v16, a0
13421330
; CHECK-D-NEXT: li a0, 1023
13431331
; CHECK-D-NEXT: vsub.vx v12, v12, a0
13441332
; CHECK-D-NEXT: vmseq.vi v0, v8, 0
@@ -3089,10 +3077,7 @@ define <vscale x 1 x i32> @cttz_zero_undef_nxv1i32(<vscale x 1 x i32> %va) {
30893077
; CHECK-D-NEXT: vand.vv v8, v8, v9
30903078
; CHECK-D-NEXT: vfwcvt.f.xu.v v9, v8
30913079
; CHECK-D-NEXT: li a0, 52
3092-
; CHECK-D-NEXT: vsetvli zero, zero, e64, m1, ta, ma
3093-
; CHECK-D-NEXT: vsrl.vx v8, v9, a0
3094-
; CHECK-D-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
3095-
; CHECK-D-NEXT: vnsrl.wi v8, v8, 0
3080+
; CHECK-D-NEXT: vnsrl.wx v8, v9, a0
30963081
; CHECK-D-NEXT: li a0, 1023
30973082
; CHECK-D-NEXT: vsub.vx v8, v8, a0
30983083
; CHECK-D-NEXT: ret
@@ -3185,12 +3170,9 @@ define <vscale x 2 x i32> @cttz_zero_undef_nxv2i32(<vscale x 2 x i32> %va) {
31853170
; CHECK-D-NEXT: vand.vv v8, v8, v9
31863171
; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v8
31873172
; CHECK-D-NEXT: li a0, 52
3188-
; CHECK-D-NEXT: vsetvli zero, zero, e64, m2, ta, ma
3189-
; CHECK-D-NEXT: vsrl.vx v8, v10, a0
3190-
; CHECK-D-NEXT: vsetvli zero, zero, e32, m1, ta, ma
3191-
; CHECK-D-NEXT: vnsrl.wi v10, v8, 0
3173+
; CHECK-D-NEXT: vnsrl.wx v8, v10, a0
31923174
; CHECK-D-NEXT: li a0, 1023
3193-
; CHECK-D-NEXT: vsub.vx v8, v10, a0
3175+
; CHECK-D-NEXT: vsub.vx v8, v8, a0
31943176
; CHECK-D-NEXT: ret
31953177
;
31963178
; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv2i32:
@@ -3281,12 +3263,9 @@ define <vscale x 4 x i32> @cttz_zero_undef_nxv4i32(<vscale x 4 x i32> %va) {
32813263
; CHECK-D-NEXT: vand.vv v8, v8, v10
32823264
; CHECK-D-NEXT: vfwcvt.f.xu.v v12, v8
32833265
; CHECK-D-NEXT: li a0, 52
3284-
; CHECK-D-NEXT: vsetvli zero, zero, e64, m4, ta, ma
3285-
; CHECK-D-NEXT: vsrl.vx v8, v12, a0
3286-
; CHECK-D-NEXT: vsetvli zero, zero, e32, m2, ta, ma
3287-
; CHECK-D-NEXT: vnsrl.wi v12, v8, 0
3266+
; CHECK-D-NEXT: vnsrl.wx v8, v12, a0
32883267
; CHECK-D-NEXT: li a0, 1023
3289-
; CHECK-D-NEXT: vsub.vx v8, v12, a0
3268+
; CHECK-D-NEXT: vsub.vx v8, v8, a0
32903269
; CHECK-D-NEXT: ret
32913270
;
32923271
; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv4i32:
@@ -3377,12 +3356,9 @@ define <vscale x 8 x i32> @cttz_zero_undef_nxv8i32(<vscale x 8 x i32> %va) {
33773356
; CHECK-D-NEXT: vand.vv v8, v8, v12
33783357
; CHECK-D-NEXT: vfwcvt.f.xu.v v16, v8
33793358
; CHECK-D-NEXT: li a0, 52
3380-
; CHECK-D-NEXT: vsetvli zero, zero, e64, m8, ta, ma
3381-
; CHECK-D-NEXT: vsrl.vx v8, v16, a0
3382-
; CHECK-D-NEXT: vsetvli zero, zero, e32, m4, ta, ma
3383-
; CHECK-D-NEXT: vnsrl.wi v16, v8, 0
3359+
; CHECK-D-NEXT: vnsrl.wx v8, v16, a0
33843360
; CHECK-D-NEXT: li a0, 1023
3385-
; CHECK-D-NEXT: vsub.vx v8, v16, a0
3361+
; CHECK-D-NEXT: vsub.vx v8, v8, a0
33863362
; CHECK-D-NEXT: ret
33873363
;
33883364
; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv8i32:

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