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ThomasRaouxThomasRaoux
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[NVPTX][NFC] Explicitly specify the matching type for Int32reg (#65527)
NFC changes to explicitly specify the type we are matching when creating Int32 reg. This will allow use to have multiple types mapping those register without causing ambigous matching.
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‎llvm/lib/Target/NVPTX/NVPTXInstrInfo.td

Lines changed: 51 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -199,11 +199,11 @@ multiclass I3<string OpcStr, SDNode OpNode> {
199199
def i32rr :
200200
NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b),
201201
!strconcat(OpcStr, "32 \t$dst, $a, $b;"),
202-
[(set Int32Regs:$dst, (OpNode Int32Regs:$a, Int32Regs:$b))]>;
202+
[(set Int32Regs:$dst, (OpNode (i32 Int32Regs:$a), (i32 Int32Regs:$b)))]>;
203203
def i32ri :
204204
NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
205205
!strconcat(OpcStr, "32 \t$dst, $a, $b;"),
206-
[(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
206+
[(set Int32Regs:$dst, (OpNode (i32 Int32Regs:$a), imm:$b))]>;
207207
def i16rr :
208208
NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int16Regs:$b),
209209
!strconcat(OpcStr, "16 \t$dst, $a, $b;"),
@@ -221,11 +221,11 @@ multiclass ADD_SUB_INT_CARRY<string OpcStr, SDNode OpNode> {
221221
def i32rr :
222222
NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b),
223223
!strconcat(OpcStr, ".s32 \t$dst, $a, $b;"),
224-
[(set Int32Regs:$dst, (OpNode Int32Regs:$a, Int32Regs:$b))]>;
224+
[(set Int32Regs:$dst, (OpNode (i32 Int32Regs:$a), (i32 Int32Regs:$b)))]>;
225225
def i32ri :
226226
NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
227227
!strconcat(OpcStr, ".s32 \t$dst, $a, $b;"),
228-
[(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
228+
[(set Int32Regs:$dst, (OpNode (i32 Int32Regs:$a), imm:$b))]>;
229229
def i64rr :
230230
NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, Int64Regs:$b),
231231
!strconcat(OpcStr, ".s64 \t$dst, $a, $b;"),
@@ -811,14 +811,14 @@ defm UREM : I3<"rem.u", urem>;
811811
// Integer absolute value. NumBits should be one minus the bit width of RC.
812812
// This idiom implements the algorithm at
813813
// http://graphics.stanford.edu/~seander/bithacks.html#IntegerAbs.
814-
multiclass ABS<RegisterClass RC, string SizeName> {
814+
multiclass ABS<ValueType T, RegisterClass RC, string SizeName> {
815815
def : NVPTXInst<(outs RC:$dst), (ins RC:$a),
816816
!strconcat("abs", SizeName, " \t$dst, $a;"),
817-
[(set RC:$dst, (abs RC:$a))]>;
817+
[(set (T RC:$dst), (abs (T RC:$a)))]>;
818818
}
819-
defm ABS_16 : ABS<Int16Regs, ".s16">;
820-
defm ABS_32 : ABS<Int32Regs, ".s32">;
821-
defm ABS_64 : ABS<Int64Regs, ".s64">;
819+
defm ABS_16 : ABS<i16, Int16Regs, ".s16">;
820+
defm ABS_32 : ABS<i32, Int32Regs, ".s32">;
821+
defm ABS_64 : ABS<i64, Int64Regs, ".s64">;
822822

823823
// Integer min/max.
824824
defm SMAX : I3<"max.s", smax>;
@@ -890,13 +890,13 @@ def : Pat<(i32 (mul_wide_unsigned Int16Regs:$a, imm:$b)),
890890
def : Pat<(i64 (mul_wide_signed i32:$a, i32:$b)),
891891
(MULWIDES64 Int32Regs:$a, Int32Regs:$b)>,
892892
Requires<[doMulWide]>;
893-
def : Pat<(i64 (mul_wide_signed Int32Regs:$a, imm:$b)),
893+
def : Pat<(i64 (mul_wide_signed (i32 Int32Regs:$a), imm:$b)),
894894
(MULWIDES64Imm Int32Regs:$a, imm:$b)>,
895895
Requires<[doMulWide]>;
896896
def : Pat<(i64 (mul_wide_unsigned i32:$a, i32:$b)),
897897
(MULWIDEU64 Int32Regs:$a, Int32Regs:$b)>,
898898
Requires<[doMulWide]>;
899-
def : Pat<(i64 (mul_wide_unsigned Int32Regs:$a, imm:$b)),
899+
def : Pat<(i64 (mul_wide_unsigned (i32 Int32Regs:$a), imm:$b)),
900900
(MULWIDEU64Imm Int32Regs:$a, imm:$b)>,
901901
Requires<[doMulWide]>;
902902

@@ -1022,22 +1022,22 @@ def MAD32rrr :
10221022
NVPTXInst<(outs Int32Regs:$dst),
10231023
(ins Int32Regs:$a, Int32Regs:$b, Int32Regs:$c),
10241024
"mad.lo.s32 \t$dst, $a, $b, $c;",
1025-
[(set Int32Regs:$dst, (imad Int32Regs:$a, Int32Regs:$b, Int32Regs:$c))]>;
1025+
[(set (i32 Int32Regs:$dst), (imad (i32 Int32Regs:$a), (i32 Int32Regs:$b), (i32 Int32Regs:$c)))]>;
10261026
def MAD32rri :
10271027
NVPTXInst<(outs Int32Regs:$dst),
10281028
(ins Int32Regs:$a, Int32Regs:$b, i32imm:$c),
10291029
"mad.lo.s32 \t$dst, $a, $b, $c;",
1030-
[(set Int32Regs:$dst, (imad Int32Regs:$a, Int32Regs:$b, imm:$c))]>;
1030+
[(set (i32 Int32Regs:$dst), (imad (i32 Int32Regs:$a), (i32 Int32Regs:$b), imm:$c))]>;
10311031
def MAD32rir :
10321032
NVPTXInst<(outs Int32Regs:$dst),
10331033
(ins Int32Regs:$a, i32imm:$b, Int32Regs:$c),
10341034
"mad.lo.s32 \t$dst, $a, $b, $c;",
1035-
[(set Int32Regs:$dst, (imad Int32Regs:$a, imm:$b, Int32Regs:$c))]>;
1035+
[(set (i32 Int32Regs:$dst), (imad (i32 Int32Regs:$a), imm:$b, (i32 Int32Regs:$c)))]>;
10361036
def MAD32rii :
10371037
NVPTXInst<(outs Int32Regs:$dst),
10381038
(ins Int32Regs:$a, i32imm:$b, i32imm:$c),
10391039
"mad.lo.s32 \t$dst, $a, $b, $c;",
1040-
[(set Int32Regs:$dst, (imad Int32Regs:$a, imm:$b, imm:$c))]>;
1040+
[(set (i32 Int32Regs:$dst), (imad (i32 Int32Regs:$a), imm:$b, imm:$c))]>;
10411041

10421042
def MAD64rrr :
10431043
NVPTXInst<(outs Int64Regs:$dst),
@@ -1067,7 +1067,7 @@ def INEG16 :
10671067
def INEG32 :
10681068
NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src),
10691069
"neg.s32 \t$dst, $src;",
1070-
[(set Int32Regs:$dst, (ineg Int32Regs:$src))]>;
1070+
[(set (i32 Int32Regs:$dst), (ineg (i32 Int32Regs:$src)))]>;
10711071
def INEG64 :
10721072
NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src),
10731073
"neg.s64 \t$dst, $src;",
@@ -1458,11 +1458,11 @@ multiclass BITWISE<string OpcStr, SDNode OpNode> {
14581458
def b32rr :
14591459
NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b),
14601460
!strconcat(OpcStr, ".b32 \t$dst, $a, $b;"),
1461-
[(set Int32Regs:$dst, (OpNode Int32Regs:$a, Int32Regs:$b))]>;
1461+
[(set Int32Regs:$dst, (OpNode (i32 Int32Regs:$a), (i32 Int32Regs:$b)))]>;
14621462
def b32ri :
14631463
NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
14641464
!strconcat(OpcStr, ".b32 \t$dst, $a, $b;"),
1465-
[(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
1465+
[(set Int32Regs:$dst, (OpNode (i32 Int32Regs:$a), imm:$b))]>;
14661466
def b64rr :
14671467
NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, Int64Regs:$b),
14681468
!strconcat(OpcStr, ".b64 \t$dst, $a, $b;"),
@@ -1485,7 +1485,7 @@ def NOT16 : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$src),
14851485
[(set Int16Regs:$dst, (not Int16Regs:$src))]>;
14861486
def NOT32 : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src),
14871487
"not.b32 \t$dst, $src;",
1488-
[(set Int32Regs:$dst, (not Int32Regs:$src))]>;
1488+
[(set (i32 Int32Regs:$dst), (not (i32 Int32Regs:$src)))]>;
14891489
def NOT64 : NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src),
14901490
"not.b64 \t$dst, $src;",
14911491
[(set Int64Regs:$dst, (not Int64Regs:$src))]>;
@@ -1499,27 +1499,27 @@ multiclass SHIFT<string OpcStr, SDNode OpNode> {
14991499
def i64rr :
15001500
NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, Int32Regs:$b),
15011501
!strconcat(OpcStr, "64 \t$dst, $a, $b;"),
1502-
[(set Int64Regs:$dst, (OpNode Int64Regs:$a, Int32Regs:$b))]>;
1502+
[(set Int64Regs:$dst, (OpNode Int64Regs:$a, (i32 Int32Regs:$b)))]>;
15031503
def i64ri :
15041504
NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, i32imm:$b),
15051505
!strconcat(OpcStr, "64 \t$dst, $a, $b;"),
15061506
[(set Int64Regs:$dst, (OpNode Int64Regs:$a, (i32 imm:$b)))]>;
15071507
def i32rr :
15081508
NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b),
15091509
!strconcat(OpcStr, "32 \t$dst, $a, $b;"),
1510-
[(set Int32Regs:$dst, (OpNode Int32Regs:$a, Int32Regs:$b))]>;
1510+
[(set Int32Regs:$dst, (OpNode (i32 Int32Regs:$a), (i32 Int32Regs:$b)))]>;
15111511
def i32ri :
15121512
NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
15131513
!strconcat(OpcStr, "32 \t$dst, $a, $b;"),
1514-
[(set Int32Regs:$dst, (OpNode Int32Regs:$a, (i32 imm:$b)))]>;
1514+
[(set Int32Regs:$dst, (OpNode (i32 Int32Regs:$a), (i32 imm:$b)))]>;
15151515
def i32ii :
15161516
NVPTXInst<(outs Int32Regs:$dst), (ins i32imm:$a, i32imm:$b),
15171517
!strconcat(OpcStr, "32 \t$dst, $a, $b;"),
15181518
[(set Int32Regs:$dst, (OpNode (i32 imm:$a), (i32 imm:$b)))]>;
15191519
def i16rr :
15201520
NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, Int32Regs:$b),
15211521
!strconcat(OpcStr, "16 \t$dst, $a, $b;"),
1522-
[(set Int16Regs:$dst, (OpNode Int16Regs:$a, Int32Regs:$b))]>;
1522+
[(set Int16Regs:$dst, (OpNode Int16Regs:$a, (i32 Int32Regs:$b)))]>;
15231523
def i16ri :
15241524
NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a, i32imm:$b),
15251525
!strconcat(OpcStr, "16 \t$dst, $a, $b;"),
@@ -1534,7 +1534,7 @@ defm SRL : SHIFT<"shr.u", srl>;
15341534
def BREV32 :
15351535
NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a),
15361536
"brev.b32 \t$dst, $a;",
1537-
[(set Int32Regs:$dst, (bitreverse Int32Regs:$a))]>;
1537+
[(set Int32Regs:$dst, (bitreverse (i32 Int32Regs:$a)))]>;
15381538
def BREV64 :
15391539
NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a),
15401540
"brev.b64 \t$dst, $a;",
@@ -1550,13 +1550,13 @@ def BREV64 :
15501550
def ROTL32imm_hw :
15511551
NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src, i32imm:$amt),
15521552
"shf.l.wrap.b32 \t$dst, $src, $src, $amt;",
1553-
[(set Int32Regs:$dst, (rotl Int32Regs:$src, (i32 imm:$amt)))]>,
1553+
[(set Int32Regs:$dst, (rotl (i32 Int32Regs:$src), (i32 imm:$amt)))]>,
15541554
Requires<[hasHWROT32]>;
15551555

15561556
def ROTL32reg_hw :
15571557
NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src, Int32Regs:$amt),
15581558
"shf.l.wrap.b32 \t$dst, $src, $src, $amt;",
1559-
[(set Int32Regs:$dst, (rotl Int32Regs:$src, Int32Regs:$amt))]>,
1559+
[(set Int32Regs:$dst, (rotl (i32 Int32Regs:$src), (i32 Int32Regs:$amt)))]>,
15601560
Requires<[hasHWROT32]>;
15611561

15621562
// 32 bit r2 = rotr r1, n
@@ -1565,13 +1565,13 @@ def ROTL32reg_hw :
15651565
def ROTR32imm_hw :
15661566
NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src, i32imm:$amt),
15671567
"shf.r.wrap.b32 \t$dst, $src, $src, $amt;",
1568-
[(set Int32Regs:$dst, (rotr Int32Regs:$src, (i32 imm:$amt)))]>,
1568+
[(set Int32Regs:$dst, (rotr (i32 Int32Regs:$src), (i32 imm:$amt)))]>,
15691569
Requires<[hasHWROT32]>;
15701570

15711571
def ROTR32reg_hw :
15721572
NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$src, Int32Regs:$amt),
15731573
"shf.r.wrap.b32 \t$dst, $src, $src, $amt;",
1574-
[(set Int32Regs:$dst, (rotr Int32Regs:$src, Int32Regs:$amt))]>,
1574+
[(set Int32Regs:$dst, (rotr (i32 Int32Regs:$src), (i32 Int32Regs:$amt)))]>,
15751575
Requires<[hasHWROT32]>;
15761576

15771577
// 32-bit software rotate by immediate. $amt2 should equal 32 - $amt1.
@@ -1591,10 +1591,10 @@ def SUB_FRM_32 : SDNodeXForm<imm, [{
15911591
return CurDAG->getTargetConstant(32 - N->getZExtValue(), SDLoc(N), MVT::i32);
15921592
}]>;
15931593

1594-
def : Pat<(rotl Int32Regs:$src, (i32 imm:$amt)),
1594+
def : Pat<(rotl (i32 Int32Regs:$src), (i32 imm:$amt)),
15951595
(ROT32imm_sw Int32Regs:$src, imm:$amt, (SUB_FRM_32 node:$amt))>,
15961596
Requires<[noHWROT32]>;
1597-
def : Pat<(rotr Int32Regs:$src, (i32 imm:$amt)),
1597+
def : Pat<(rotr (i32 Int32Regs:$src), (i32 imm:$amt)),
15981598
(ROT32imm_sw Int32Regs:$src, (SUB_FRM_32 node:$amt), imm:$amt)>,
15991599
Requires<[noHWROT32]>;
16001600

@@ -1610,7 +1610,7 @@ def ROTL32reg_sw :
16101610
"shr.b32 \t%rhs, $src, %amt2;\n\t"
16111611
"add.u32 \t$dst, %lhs, %rhs;\n\t"
16121612
"}}",
1613-
[(set Int32Regs:$dst, (rotl Int32Regs:$src, Int32Regs:$amt))]>,
1613+
[(set Int32Regs:$dst, (rotl (i32 Int32Regs:$src), (i32 Int32Regs:$amt)))]>,
16141614
Requires<[noHWROT32]>;
16151615

16161616
// 32-bit software rotate right by register.
@@ -1625,7 +1625,7 @@ def ROTR32reg_sw :
16251625
"shl.b32 \t%rhs, $src, %amt2;\n\t"
16261626
"add.u32 \t$dst, %lhs, %rhs;\n\t"
16271627
"}}",
1628-
[(set Int32Regs:$dst, (rotr Int32Regs:$src, Int32Regs:$amt))]>,
1628+
[(set Int32Regs:$dst, (rotr (i32 Int32Regs:$src), (i32 Int32Regs:$amt)))]>,
16291629
Requires<[noHWROT32]>;
16301630

16311631
// 64-bit software rotate by immediate. $amt2 should equal 64 - $amt1.
@@ -1662,7 +1662,7 @@ def ROTL64reg_sw :
16621662
"shr.b64 \t%rhs, $src, %amt2;\n\t"
16631663
"add.u64 \t$dst, %lhs, %rhs;\n\t"
16641664
"}}",
1665-
[(set Int64Regs:$dst, (rotl Int64Regs:$src, Int32Regs:$amt))]>;
1665+
[(set Int64Regs:$dst, (rotl Int64Regs:$src, (i32 Int32Regs:$amt)))]>;
16661666

16671667
def ROTR64reg_sw :
16681668
NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$src, Int32Regs:$amt),
@@ -1675,7 +1675,7 @@ def ROTR64reg_sw :
16751675
"shl.b64 \t%rhs, $src, %amt2;\n\t"
16761676
"add.u64 \t$dst, %lhs, %rhs;\n\t"
16771677
"}}",
1678-
[(set Int64Regs:$dst, (rotr Int64Regs:$src, Int32Regs:$amt))]>;
1678+
[(set Int64Regs:$dst, (rotr Int64Regs:$src, (i32 Int32Regs:$amt)))]>;
16791679

16801680
//
16811681
// Funnnel shift in clamp mode
@@ -1691,14 +1691,14 @@ def FUNSHFLCLAMP :
16911691
(ins Int32Regs:$lo, Int32Regs:$hi, Int32Regs:$amt),
16921692
"shf.l.clamp.b32 \t$dst, $lo, $hi, $amt;",
16931693
[(set Int32Regs:$dst,
1694-
(FUN_SHFL_CLAMP Int32Regs:$lo, Int32Regs:$hi, Int32Regs:$amt))]>;
1694+
(FUN_SHFL_CLAMP (i32 Int32Regs:$lo), (i32 Int32Regs:$hi), (i32 Int32Regs:$amt)))]>;
16951695

16961696
def FUNSHFRCLAMP :
16971697
NVPTXInst<(outs Int32Regs:$dst),
16981698
(ins Int32Regs:$lo, Int32Regs:$hi, Int32Regs:$amt),
16991699
"shf.r.clamp.b32 \t$dst, $lo, $hi, $amt;",
17001700
[(set Int32Regs:$dst,
1701-
(FUN_SHFR_CLAMP Int32Regs:$lo, Int32Regs:$hi, Int32Regs:$amt))]>;
1701+
(FUN_SHFR_CLAMP (i32 Int32Regs:$lo), (i32 Int32Regs:$hi), (i32 Int32Regs:$amt)))]>;
17021702

17031703
//
17041704
// BFE - bit-field extract
@@ -1915,7 +1915,7 @@ def IMOV16ri : NVPTXInst<(outs Int16Regs:$dst), (ins i16imm:$src),
19151915
[(set Int16Regs:$dst, imm:$src)]>;
19161916
def IMOV32ri : NVPTXInst<(outs Int32Regs:$dst), (ins i32imm:$src),
19171917
"mov.u32 \t$dst, $src;",
1918-
[(set Int32Regs:$dst, imm:$src)]>;
1918+
[(set (i32 Int32Regs:$dst), imm:$src)]>;
19191919
def IMOV64ri : NVPTXInst<(outs Int64Regs:$dst), (ins i64imm:$src),
19201920
"mov.u64 \t$dst, $src;",
19211921
[(set Int64Regs:$dst, imm:$src)]>;
@@ -1978,9 +1978,9 @@ multiclass ISET_FORMAT<PatFrag OpNode, PatLeaf Mode,
19781978
// i32 -> pred
19791979
def : Pat<(i1 (OpNode i32:$a, i32:$b)),
19801980
(setp_32rr Int32Regs:$a, Int32Regs:$b, Mode)>;
1981-
def : Pat<(i1 (OpNode Int32Regs:$a, imm:$b)),
1981+
def : Pat<(i1 (OpNode (i32 Int32Regs:$a), imm:$b)),
19821982
(setp_32ri Int32Regs:$a, imm:$b, Mode)>;
1983-
def : Pat<(i1 (OpNode imm:$a, Int32Regs:$b)),
1983+
def : Pat<(i1 (OpNode imm:$a, (i32 Int32Regs:$b))),
19841984
(setp_32ir imm:$a, Int32Regs:$b, Mode)>;
19851985
// i64 -> pred
19861986
def : Pat<(i1 (OpNode Int64Regs:$a, Int64Regs:$b)),
@@ -2000,9 +2000,9 @@ multiclass ISET_FORMAT<PatFrag OpNode, PatLeaf Mode,
20002000
// i32 -> i32
20012001
def : Pat<(i32 (OpNode i32:$a, i32:$b)),
20022002
(set_32rr Int32Regs:$a, Int32Regs:$b, Mode)>;
2003-
def : Pat<(i32 (OpNode Int32Regs:$a, imm:$b)),
2003+
def : Pat<(i32 (OpNode (i32 Int32Regs:$a), imm:$b)),
20042004
(set_32ri Int32Regs:$a, imm:$b, Mode)>;
2005-
def : Pat<(i32 (OpNode imm:$a, Int32Regs:$b)),
2005+
def : Pat<(i32 (OpNode imm:$a, (i32 Int32Regs:$b))),
20062006
(set_32ir imm:$a, Int32Regs:$b, Mode)>;
20072007
// i64 -> i32
20082008
def : Pat<(i32 (OpNode Int64Regs:$a, Int64Regs:$b)),
@@ -3207,25 +3207,25 @@ def : Pat<(sext_inreg Int64Regs:$a, i32), (CVT_INREG_s64_s32 Int64Regs:$a)>;
32073207

32083208

32093209
// Select instructions with 32-bit predicates
3210-
def : Pat<(select Int32Regs:$pred, i16:$a, i16:$b),
3210+
def : Pat<(select (i32 Int32Regs:$pred), i16:$a, i16:$b),
32113211
(SELP_b16rr Int16Regs:$a, Int16Regs:$b,
32123212
(SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
3213-
def : Pat<(select Int32Regs:$pred, i32:$a, i32:$b),
3213+
def : Pat<(select (i32 Int32Regs:$pred), i32:$a, i32:$b),
32143214
(SELP_b32rr Int32Regs:$a, Int32Regs:$b,
32153215
(SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
3216-
def : Pat<(select Int32Regs:$pred, Int64Regs:$a, Int64Regs:$b),
3216+
def : Pat<(select (i32 Int32Regs:$pred), Int64Regs:$a, Int64Regs:$b),
32173217
(SELP_b64rr Int64Regs:$a, Int64Regs:$b,
32183218
(SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
3219-
def : Pat<(select Int32Regs:$pred, (f16 Int16Regs:$a), (f16 Int16Regs:$b)),
3219+
def : Pat<(select (i32 Int32Regs:$pred), (f16 Int16Regs:$a), (f16 Int16Regs:$b)),
32203220
(SELP_f16rr Int16Regs:$a, Int16Regs:$b,
32213221
(SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
3222-
def : Pat<(select Int32Regs:$pred, (bf16 Int16Regs:$a), (bf16 Int16Regs:$b)),
3222+
def : Pat<(select (i32 Int32Regs:$pred), (bf16 Int16Regs:$a), (bf16 Int16Regs:$b)),
32233223
(SELP_bf16rr Int16Regs:$a, Int16Regs:$b,
32243224
(SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
3225-
def : Pat<(select Int32Regs:$pred, Float32Regs:$a, Float32Regs:$b),
3225+
def : Pat<(select (i32 Int32Regs:$pred), Float32Regs:$a, Float32Regs:$b),
32263226
(SELP_f32rr Float32Regs:$a, Float32Regs:$b,
32273227
(SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
3228-
def : Pat<(select Int32Regs:$pred, Float64Regs:$a, Float64Regs:$b),
3228+
def : Pat<(select (i32 Int32Regs:$pred), Float64Regs:$a, Float64Regs:$b),
32293229
(SELP_f64rr Float64Regs:$a, Float64Regs:$b,
32303230
(SETP_b32ri (ANDb32ri Int32Regs:$pred, 1), 1, CmpEQ))>;
32313231

@@ -3309,7 +3309,7 @@ let hasSideEffects = false in {
33093309
}
33103310

33113311
// 32-bit has a direct PTX instruction
3312-
def : Pat<(ctlz Int32Regs:$a), (CLZr32 Int32Regs:$a)>;
3312+
def : Pat<(i32 (ctlz (i32 Int32Regs:$a))), (CLZr32 Int32Regs:$a)>;
33133313

33143314
// The return type of the ctlz ISD node is the same as its input, but the PTX
33153315
// ctz instruction always returns a 32-bit value. For ctlz.i64, convert the
@@ -3347,7 +3347,7 @@ let hasSideEffects = false in {
33473347
}
33483348

33493349
// 32-bit has a direct PTX instruction
3350-
def : Pat<(ctpop Int32Regs:$a), (POPCr32 Int32Regs:$a)>;
3350+
def : Pat<(i32 (ctpop (i32 Int32Regs:$a))), (POPCr32 Int32Regs:$a)>;
33513351

33523352
// For 64-bit, the result in PTX is actually 32-bit so we zero-extend to 64-bit
33533353
// to match the LLVM semantics. Just as with ctlz.i64, we provide a second
@@ -3460,7 +3460,7 @@ let isTerminator=1 in {
34603460
"bra.uni \t$target;", [(br bb:$target)]>;
34613461
}
34623462

3463-
def : Pat<(brcond Int32Regs:$a, bb:$target),
3463+
def : Pat<(brcond (i32 Int32Regs:$a), bb:$target),
34643464
(CBranch (SETP_u32ri Int32Regs:$a, 0, CmpNE), bb:$target)>;
34653465

34663466
// SelectionDAGBuilder::visitSWitchCase() will invert the condition of a

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