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Fixup! Sink ordered reduction into ISD::FAdd.
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llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1552,13 +1552,6 @@ RISCVTTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
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}
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// IR Reduction is composed by two vmv and one rvv reduction instruction.
1555-
if (TTI::requiresOrderedReduction(FMF) && ElementTy->isFloatingPointTy()) {
1556-
Opcodes.push_back(RISCV::VFMV_S_F);
1557-
for (unsigned i = 0; i < LT.first.getValue(); i++)
1558-
Opcodes.push_back(RISCV::VFREDOSUM_VS);
1559-
Opcodes.push_back(RISCV::VFMV_F_S);
1560-
return getRISCVInstructionCost(Opcodes, LT.second, CostKind);
1561-
}
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unsigned SplitOp;
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switch (ISD) {
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case ISD::ADD:
@@ -1578,6 +1571,13 @@ RISCVTTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
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Opcodes = {RISCV::VMV_S_X, RISCV::VREDAND_VS, RISCV::VMV_X_S};
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break;
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case ISD::FADD:
1574+
if (TTI::requiresOrderedReduction(FMF)) {
1575+
Opcodes.push_back(RISCV::VFMV_S_F);
1576+
for (unsigned i = 0; i < LT.first.getValue(); i++)
1577+
Opcodes.push_back(RISCV::VFREDOSUM_VS);
1578+
Opcodes.push_back(RISCV::VFMV_F_S);
1579+
return getRISCVInstructionCost(Opcodes, LT.second, CostKind);
1580+
}
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// We can't promote f16/bf16 fadd reductions.
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if ((LT.second.getVectorElementType() == MVT::f16 &&
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!ST->hasVInstructionsF16()) ||

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