@@ -2400,10 +2400,11 @@ void AArch64TargetLowering::computeKnownBitsForTargetNode(
2400
2400
}
2401
2401
case AArch64ISD::BICi: {
2402
2402
// Compute the bit cleared value.
2403
- uint64_t Mask =
2404
- ~(Op->getConstantOperandVal(1) << Op->getConstantOperandVal(2));
2403
+ APInt Mask =
2404
+ ~(Op->getConstantOperandAPInt(1) << Op->getConstantOperandAPInt(2))
2405
+ .trunc(Known.getBitWidth());
2405
2406
Known = DAG.computeKnownBits(Op->getOperand(0), Depth + 1);
2406
- Known &= KnownBits::makeConstant(APInt(Known.getBitWidth(), Mask) );
2407
+ Known &= KnownBits::makeConstant(Mask);
2407
2408
break;
2408
2409
}
2409
2410
case AArch64ISD::VLSHR: {
@@ -12839,7 +12840,8 @@ static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
12839
12840
// Benefit form APInt to handle overflow when calculating expected element.
12840
12841
unsigned NumElts = VT.getVectorNumElements();
12841
12842
unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
12842
- APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
12843
+ APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1, /*isSigned=*/false,
12844
+ /*implicitTrunc=*/true);
12843
12845
// The following shuffle indices must be the successive elements after the
12844
12846
// first real element.
12845
12847
bool FoundWrongElt = std::any_of(FirstRealElt + 1, M.end(), [&](int Elt) {
@@ -14306,9 +14308,9 @@ static SDValue NormalizeBuildVector(SDValue Op,
14306
14308
// (with operands cast to integers), then the only possibilities
14307
14309
// are constants and UNDEFs.
14308
14310
if (auto *CstLane = dyn_cast<ConstantSDNode>(Lane)) {
14309
- APInt LowBits(EltTy.getSizeInBits(),
14310
- CstLane->getZExtValue());
14311
- Lane = DAG.getConstant(LowBits.getZExtValue(), dl, MVT::i32);
14311
+ Lane = DAG.getConstant(
14312
+ CstLane->getAPIntValue().trunc(EltTy.getSizeInBits()).getZExtValue(),
14313
+ dl, MVT::i32);
14312
14314
} else if (Lane.getNode()->isUndef()) {
14313
14315
Lane = DAG.getUNDEF(MVT::i32);
14314
14316
} else {
@@ -23713,7 +23715,7 @@ static bool findMoreOptimalIndexType(const MaskedGatherScatterSDNode *N,
23713
23715
EVT NewIndexVT = IndexVT.changeVectorElementType(MVT::i32);
23714
23716
// Stride does not scale explicitly by 'Scale', because it happens in
23715
23717
// the gather/scatter addressing mode.
23716
- Index = DAG.getStepVector(SDLoc(N), NewIndexVT, APInt(32, Stride));
23718
+ Index = DAG.getStepVector(SDLoc(N), NewIndexVT, APInt(32, Stride, true ));
23717
23719
return true;
23718
23720
}
23719
23721
@@ -28727,7 +28729,7 @@ static SDValue GenerateFixedLengthSVETBL(SDValue Op, SDValue Op1, SDValue Op2,
28727
28729
unsigned BitsPerElt = VTOp1.getVectorElementType().getSizeInBits();
28728
28730
unsigned IndexLen = MinSVESize / BitsPerElt;
28729
28731
unsigned ElementsPerVectorReg = VTOp1.getVectorNumElements();
28730
- uint64_t MaxOffset = APInt (BitsPerElt, -1, false).getZExtValue( );
28732
+ uint64_t MaxOffset = maxUIntN (BitsPerElt);
28731
28733
EVT MaskEltType = VTOp1.getVectorElementType().changeTypeToInteger();
28732
28734
EVT MaskType = EVT::getVectorVT(*DAG.getContext(), MaskEltType, IndexLen);
28733
28735
bool MinMaxEqual = (MinSVESize == MaxSVESize);
@@ -29085,16 +29087,14 @@ bool AArch64TargetLowering::SimplifyDemandedBitsForTargetNode(
29085
29087
KnownBits KnownOp0 =
29086
29088
TLO.DAG.computeKnownBits(Op0, OriginalDemandedElts, Depth + 1);
29087
29089
// Op0 &= ~(ConstantOperandVal(1) << ConstantOperandVal(2))
29088
- uint64_t BitsToClear = Op->getConstantOperandVal(1)
29089
- << Op->getConstantOperandVal(2);
29090
+ APInt BitsToClear =
29091
+ (Op->getConstantOperandAPInt(1) << Op->getConstantOperandAPInt(2))
29092
+ .trunc(KnownOp0.getBitWidth());
29090
29093
APInt AlreadyZeroedBitsToClear = BitsToClear & KnownOp0.Zero;
29091
- if (APInt(Known.getBitWidth(), BitsToClear)
29092
- .isSubsetOf(AlreadyZeroedBitsToClear))
29094
+ if (BitsToClear.isSubsetOf(AlreadyZeroedBitsToClear))
29093
29095
return TLO.CombineTo(Op, Op0);
29094
29096
29095
- Known = KnownOp0 &
29096
- KnownBits::makeConstant(APInt(Known.getBitWidth(), ~BitsToClear));
29097
-
29097
+ Known = KnownOp0 & KnownBits::makeConstant(~BitsToClear);
29098
29098
return false;
29099
29099
}
29100
29100
case ISD::INTRINSIC_WO_CHAIN: {
0 commit comments