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[AArch64] Add the Ampere1B core
The Ampere1B is Ampere's third-generation core implementing a superscalar, out-of-order microarchitecture with nested virtualization, speculative side-channel mitigation and architectural support for defense against ROP/JOP style software attacks. Ampere1B is an ARMv8.7+ implementation, adding support for the FEAT WFxT, FEAT CSSC, FEAT PAN3 and FEAT AFP extensions. It also includes all features of the second-generation Ampere1A, such as the Memory Tagging Extension and SM3/SM4 cryptography instructions. Signed-off-by: Philipp Tomsich <[email protected]>
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‎clang/test/Driver/aarch64-cssc.c

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@@ -9,6 +9,7 @@
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// RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf -march=armv9.4-a %s 2>&1 | FileCheck %s
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// RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf -march=armv9.4-a+cssc %s 2>&1 | FileCheck %s
1111
// RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf -march=armv9.4-a+nocssc %s 2>&1 | FileCheck %s --check-prefix=NO_CSSC
12+
// RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf -mcpu=ampere1b %s 2>&1 | FileCheck %s
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// CHECK: "target-features"="{{.*}},+cssc
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// NO_CSSC: "target-features"="{{.*}},-cssc

‎clang/test/Misc/target-invalid-cpu-note.c

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@@ -5,11 +5,11 @@
55

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// RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AARCH64
77
// AARCH64: error: unknown target CPU 'not-a-cpu'
8-
// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, cobalt-100, grace{{$}}
8+
// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}}
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// RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_AARCH64
1111
// TUNE_AARCH64: error: unknown target CPU 'not-a-cpu'
12-
// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, cobalt-100, grace{{$}}
12+
// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}}
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// RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86
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// X86: error: unknown target CPU 'not-a-cpu'

‎llvm/include/llvm/TargetParser/AArch64TargetParser.h

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@@ -805,6 +805,12 @@ inline constexpr CpuInfo CpuInfos[] = {
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{AArch64::AEK_FP16, AArch64::AEK_RAND, AArch64::AEK_SM4,
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AArch64::AEK_SHA3, AArch64::AEK_SHA2, AArch64::AEK_AES,
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AArch64::AEK_MTE, AArch64::AEK_SB, AArch64::AEK_SSBS}))},
808+
{"ampere1b", ARMV8_7A,
809+
(AArch64::ExtensionBitset({AArch64::AEK_FP16, AArch64::AEK_RAND,
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AArch64::AEK_SM4, AArch64::AEK_SHA3,
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AArch64::AEK_SHA2, AArch64::AEK_AES,
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AArch64::AEK_MTE, AArch64::AEK_SB,
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AArch64::AEK_SSBS, AArch64::AEK_CSSC}))},
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};
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// An alias for a CPU.

‎llvm/lib/Target/AArch64/AArch64.td

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@@ -1376,6 +1376,24 @@ def TuneAmpere1A : SubtargetFeature<"ampere1a", "ARMProcFamily", "Ampere1A",
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FeatureLdpAlignedOnly,
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FeatureStpAlignedOnly]>;
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def TuneAmpere1B : SubtargetFeature<"ampere1b", "ARMProcFamily", "Ampere1B",
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"Ampere Computing Ampere-1B processors", [
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FeaturePostRAScheduler,
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FeatureFuseAES,
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FeatureFuseAdrpAdd,
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FeatureAddrLSLFast,
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FeatureALULSLFast,
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FeatureAggressiveFMA,
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FeatureArithmeticBccFusion,
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FeatureCmpBccFusion,
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FeatureFuseAddress,
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FeatureFuseLiterals,
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FeatureStorePairSuppress,
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FeatureEnableSelectOptimize,
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FeaturePredictableSelectIsExpensive,
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FeatureLdpAlignedOnly,
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FeatureStpAlignedOnly]>;
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13791397
def ProcessorFeatures {
13801398
list<SubtargetFeature> A53 = [HasV8_0aOps, FeatureCRC, FeatureCrypto,
13811399
FeatureFPARMv8, FeatureNEON, FeaturePerfMon];
@@ -1530,6 +1548,11 @@ def ProcessorFeatures {
15301548
FeatureMTE, FeatureSSBS, FeatureRandGen,
15311549
FeatureSB, FeatureSM4, FeatureSHA2,
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FeatureSHA3, FeatureAES];
1551+
list<SubtargetFeature> Ampere1B = [HasV8_7aOps, FeatureNEON, FeaturePerfMon,
1552+
FeatureMTE, FeatureSSBS, FeatureRandGen,
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FeatureSB, FeatureSM4, FeatureSHA2,
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FeatureSHA3, FeatureAES, FeatureCSSC,
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FeatureWFxT];
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15341557
// ETE and TRBE are future architecture extensions. We temporarily enable them
15351558
// by default for users targeting generic AArch64. The extensions do not
@@ -1697,6 +1720,9 @@ def : ProcessorModel<"ampere1", Ampere1Model, ProcessorFeatures.Ampere1,
16971720
def : ProcessorModel<"ampere1a", Ampere1Model, ProcessorFeatures.Ampere1A,
16981721
[TuneAmpere1A]>;
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1723+
def : ProcessorModel<"ampere1b", Ampere1Model, ProcessorFeatures.Ampere1B,
1724+
[TuneAmpere1B]>;
1725+
17001726
//===----------------------------------------------------------------------===//
17011727
// Assembly parser
17021728
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/AArch64Subtarget.cpp

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@@ -296,6 +296,7 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) {
296296
break;
297297
case Ampere1:
298298
case Ampere1A:
299+
case Ampere1B:
299300
CacheLineSize = 64;
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PrefFunctionAlignment = Align(64);
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PrefLoopAlignment = Align(64);

‎llvm/lib/Target/AArch64/AArch64Subtarget.h

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@@ -42,6 +42,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
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A64FX,
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Ampere1,
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Ampere1A,
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Ampere1B,
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AppleA7,
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AppleA10,
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AppleA11,

‎llvm/lib/TargetParser/Host.cpp

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@@ -321,6 +321,7 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) {
321321
return StringSwitch<const char *>(Part)
322322
.Case("0xac3", "ampere1")
323323
.Case("0xac4", "ampere1a")
324+
.Case("0xac5", "ampere1b")
324325
.Default("generic");
325326
}
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‎llvm/test/CodeGen/AArch64/cpus.ll

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@@ -37,6 +37,7 @@
3737
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=a64fx 2>&1 | FileCheck %s
3838
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=ampere1 2>&1 | FileCheck %s
3939
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=ampere1a 2>&1 | FileCheck %s
40+
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=ampere1b 2>&1 | FileCheck %s
4041
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=invalidcpu 2>&1 | FileCheck %s --check-prefix=INVALID
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; CHECK-NOT: {{.*}} is not a recognized processor for this target

‎llvm/test/CodeGen/AArch64/neon-dot-product.ll

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@@ -7,6 +7,7 @@
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; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=neoverse-n2 < %s | FileCheck %s
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; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=ampere1 < %s | FileCheck %s
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; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=ampere1a < %s | FileCheck %s
10+
; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=ampere1b < %s | FileCheck %s
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declare <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32>, <8 x i8>, <8 x i8>)
1213
declare <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>)

‎llvm/test/CodeGen/AArch64/remat.ll

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@@ -26,6 +26,7 @@
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; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx3t110 -o - %s | FileCheck %s
2727
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=ampere1 -o - %s | FileCheck %s
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; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=ampere1a -o - %s | FileCheck %s
29+
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=ampere1b -o - %s | FileCheck %s
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3031
%X = type { i64, i64, i64 }
3132
declare void @f(ptr)

‎llvm/test/MC/AArch64/armv8.2a-dotprod.s

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@@ -15,6 +15,7 @@
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// RUN: llvm-mc -triple aarch64 -mattr=+v8r,+dotprod -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
1616
// RUN: llvm-mc -triple aarch64 -mcpu=ampere1 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
1717
// RUN: llvm-mc -triple aarch64 -mcpu=ampere1a -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
18+
// RUN: llvm-mc -triple aarch64 -mcpu=ampere1b -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DOTPROD
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1920
// RUN: not llvm-mc -triple aarch64 -mattr=+v8.2a -show-encoding < %s 2> %t
2021
// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
@@ -42,6 +43,8 @@
4243
// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
4344
// RUN: not llvm-mc -triple aarch64 -mcpu=ampere1a -mattr=-dotprod -show-encoding < %s 2> %t
4445
// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
46+
// RUN: not llvm-mc -triple aarch64 -mcpu=ampere1b -mattr=-dotprod -show-encoding < %s 2> %t
47+
// RUN: FileCheck --check-prefix=CHECK-NO-DOTPROD < %t %s
4548

4649
udot v0.2s, v1.8b, v2.8b
4750
sdot v0.2s, v1.8b, v2.8b

‎llvm/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt

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@@ -14,6 +14,7 @@
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# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=neoverse-n2 --disassemble < %s | FileCheck %s
1515
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=ampere1 --disassemble < %s | FileCheck %s
1616
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=ampere1a --disassemble < %s | FileCheck %s
17+
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mcpu=ampere1b --disassemble < %s | FileCheck %s
1718

1819
# CHECK: ldaprb w0, [x0]
1920
# CHECK: ldaprh w0, [x0]

‎llvm/unittests/TargetParser/Host.cpp

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@@ -122,6 +122,9 @@ TEST(getLinuxHostCPUName, AArch64) {
122122
EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0xc0\n"
123123
"CPU part : 0xac4"),
124124
"ampere1a");
125+
EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0xc0\n"
126+
"CPU part : 0xac5"),
127+
"ampere1b");
125128

126129
// MSM8992/4 weirdness
127130
StringRef MSM8992ProcCpuInfo = R"(

‎llvm/unittests/TargetParser/TargetParserTest.cpp

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Original file line numberDiff line numberDiff line change
@@ -1600,6 +1600,18 @@ INSTANTIATE_TEST_SUITE_P(
16001600
AArch64::AEK_MTE, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
16011601
AArch64::AEK_PAUTH})),
16021602
"8.6-A"),
1603+
ARMCPUTestParams<AArch64::ExtensionBitset>(
1604+
"ampere1b", "armv8.7-a", "crypto-neon-fp-armv8",
1605+
(AArch64::ExtensionBitset(
1606+
{AArch64::AEK_CRC, AArch64::AEK_FP, AArch64::AEK_FP16,
1607+
AArch64::AEK_SIMD, AArch64::AEK_RAS, AArch64::AEK_LSE,
1608+
AArch64::AEK_RDM, AArch64::AEK_RCPC, AArch64::AEK_DOTPROD,
1609+
AArch64::AEK_SM4, AArch64::AEK_SHA3, AArch64::AEK_BF16,
1610+
AArch64::AEK_SHA2, AArch64::AEK_AES, AArch64::AEK_I8MM,
1611+
AArch64::AEK_SSBS, AArch64::AEK_SB, AArch64::AEK_RAND,
1612+
AArch64::AEK_MTE, AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
1613+
AArch64::AEK_PAUTH, AArch64::AEK_CSSC})),
1614+
"8.7-A"),
16031615
ARMCPUTestParams<AArch64::ExtensionBitset>(
16041616
"neoverse-512tvb", "armv8.4-a", "crypto-neon-fp-armv8",
16051617
(AArch64::ExtensionBitset(
@@ -1679,7 +1691,7 @@ INSTANTIATE_TEST_SUITE_P(
16791691
ARMCPUTestParams<AArch64::ExtensionBitset>::PrintToStringParamName);
16801692

16811693
// Note: number of CPUs includes aliases.
1682-
static constexpr unsigned NumAArch64CPUArchs = 68;
1694+
static constexpr unsigned NumAArch64CPUArchs = 69;
16831695

16841696
TEST(TargetParserTest, testAArch64CPUArchList) {
16851697
SmallVector<StringRef, NumAArch64CPUArchs> List;

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