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[CodeGen] Provide MachineFunction::hasUnsafeFPMath
Address #27735 incrementally. New code should use `MachineFunction::hasUnsafeFPMath`.
1 parent dd3edc8 commit 25a2cb2

21 files changed

+91
-83
lines changed

‎llvm/include/llvm/CodeGen/MachineFunction.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -820,6 +820,10 @@ class LLVM_ABI MachineFunction {
820820
/// True if this function needs frame moves for debug or exceptions.
821821
bool needsFrameMoves() const;
822822

823+
/// True if function attribute unsafe-fp-math is true or
824+
/// --enable-unsafe-fp-math is passed.
825+
bool hasUnsafeFPMath() const;
826+
823827
/// Get the function properties
824828
const MachineFunctionProperties &getProperties() const { return Properties; }
825829
MachineFunctionProperties &getProperties() { return Properties; }

‎llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5774,7 +5774,7 @@ bool CombinerHelper::canCombineFMadOrFMA(MachineInstr &MI,
57745774
LLT DstType = MRI.getType(MI.getOperand(0).getReg());
57755775

57765776
if (CanReassociate &&
5777-
!(Options.UnsafeFPMath || MI.getFlag(MachineInstr::MIFlag::FmReassoc)))
5777+
!(MF->hasUnsafeFPMath() || MI.getFlag(MachineInstr::MIFlag::FmReassoc)))
57785778
return false;
57795779

57805780
// Floating-point multiply-add with intermediate rounding.
@@ -5787,7 +5787,7 @@ bool CombinerHelper::canCombineFMadOrFMA(MachineInstr &MI,
57875787
return false;
57885788

57895789
AllowFusionGlobally = Options.AllowFPOpFusion == FPOpFusion::Fast ||
5790-
Options.UnsafeFPMath || HasFMAD;
5790+
MF->hasUnsafeFPMath() || HasFMAD;
57915791
// If the addition is not contractable, do not combine.
57925792
if (!AllowFusionGlobally && !MI.getFlag(MachineInstr::MIFlag::FmContract))
57935793
return false;

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7879,7 +7879,7 @@ LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) {
78797879
if (MRI.getType(Src).isVector()) // TODO: Handle vectors directly.
78807880
return UnableToLegalize;
78817881

7882-
if (MIRBuilder.getMF().getTarget().Options.UnsafeFPMath) {
7882+
if (MIRBuilder.getMF().hasUnsafeFPMath()) {
78837883
unsigned Flags = MI.getFlags();
78847884
auto Src32 = MIRBuilder.buildFPTrunc(S32, Src, Flags);
78857885
MIRBuilder.buildFPTrunc(Dst, Src32, Flags);

‎llvm/lib/CodeGen/MachineFunction.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -699,6 +699,11 @@ bool MachineFunction::needsFrameMoves() const {
699699
!F.getParent()->debug_compile_units().empty();
700700
}
701701

702+
/// True if function attribute unsafe-fp-math is true.
703+
bool MachineFunction::hasUnsafeFPMath() const {
704+
return F.getFnAttribute("unsafe-fp-math").getValueAsBool();
705+
}
706+
702707
namespace llvm {
703708

704709
template<>

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 37 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -16280,15 +16280,6 @@ ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
1628016280
return DAG.getBuildVector(VT, DL, Ops);
1628116281
}
1628216282

16283-
// Returns true if floating point contraction is allowed on the FMUL-SDValue
16284-
// `N`
16285-
static bool isContractableFMUL(const TargetOptions &Options, SDValue N) {
16286-
assert(N.getOpcode() == ISD::FMUL);
16287-
16288-
return Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath ||
16289-
N->getFlags().hasAllowContract();
16290-
}
16291-
1629216283
// Returns true if `N` can assume no infinities involved in its computation.
1629316284
static bool hasNoInfs(const TargetOptions &Options, SDValue N) {
1629416285
return Options.NoInfsFPMath || N->getFlags().hasNoInfs();
@@ -16320,8 +16311,9 @@ SDValue DAGCombiner::visitFADDForFMACombine(SDNode *N) {
1632016311
if (!HasFMAD && !HasFMA)
1632116312
return SDValue();
1632216313

16323-
bool AllowFusionGlobally = (Options.AllowFPOpFusion == FPOpFusion::Fast ||
16324-
Options.UnsafeFPMath || HasFMAD);
16314+
bool UnsafeFPMath = DAG.getMachineFunction().hasUnsafeFPMath();
16315+
bool AllowFusionGlobally =
16316+
(Options.AllowFPOpFusion == FPOpFusion::Fast || UnsafeFPMath || HasFMAD);
1632516317
// If the addition is not contractable, do not combine.
1632616318
if (!AllowFusionGlobally && !N->getFlags().hasAllowContract())
1632716319
return SDValue();
@@ -16379,8 +16371,7 @@ SDValue DAGCombiner::visitFADDForFMACombine(SDNode *N) {
1637916371
// fadd (G, (fma A, B, (fma (C, D, (fmul (E, F)))))) -->
1638016372
// fma A, B, (fma C, D, fma (E, F, G)).
1638116373
// This requires reassociation because it changes the order of operations.
16382-
bool CanReassociate =
16383-
Options.UnsafeFPMath || N->getFlags().hasAllowReassociation();
16374+
bool CanReassociate = UnsafeFPMath || N->getFlags().hasAllowReassociation();
1638416375
if (CanReassociate) {
1638516376
SDValue FMA, E;
1638616377
if (isFusedOp(N0) && N0.hasOneUse()) {
@@ -16558,8 +16549,9 @@ SDValue DAGCombiner::visitFSUBForFMACombine(SDNode *N) {
1655816549
return SDValue();
1655916550

1656016551
const SDNodeFlags Flags = N->getFlags();
16561-
bool AllowFusionGlobally = (Options.AllowFPOpFusion == FPOpFusion::Fast ||
16562-
Options.UnsafeFPMath || HasFMAD);
16552+
bool UnsafeFPMath = DAG.getMachineFunction().hasUnsafeFPMath();
16553+
bool AllowFusionGlobally =
16554+
(Options.AllowFPOpFusion == FPOpFusion::Fast || UnsafeFPMath || HasFMAD);
1656316555

1656416556
// If the subtraction is not contractable, do not combine.
1656516557
if (!AllowFusionGlobally && !N->getFlags().hasAllowContract())
@@ -16714,8 +16706,8 @@ SDValue DAGCombiner::visitFSUBForFMACombine(SDNode *N) {
1671416706
}
1671516707
}
1671616708

16717-
auto isReassociable = [&Options](SDNode *N) {
16718-
return Options.UnsafeFPMath || N->getFlags().hasAllowReassociation();
16709+
auto isReassociable = [UnsafeFPMath](SDNode *N) {
16710+
return UnsafeFPMath || N->getFlags().hasAllowReassociation();
1671916711
};
1672016712

1672116713
auto isContractableAndReassociableFMUL = [&isContractableFMUL,
@@ -16729,7 +16721,7 @@ SDValue DAGCombiner::visitFSUBForFMACombine(SDNode *N) {
1672916721

1673016722
// More folding opportunities when target permits.
1673116723
if (Aggressive && isReassociable(N)) {
16732-
bool CanFuse = Options.UnsafeFPMath || N->getFlags().hasAllowContract();
16724+
bool CanFuse = UnsafeFPMath || N->getFlags().hasAllowContract();
1673316725
// fold (fsub (fma x, y, (fmul u, v)), z)
1673416726
// -> (fma x, y (fma u, v, (fneg z)))
1673516727
if (CanFuse && isFusedOp(N0) &&
@@ -16878,6 +16870,16 @@ SDValue DAGCombiner::visitFMULForFMADistributiveCombine(SDNode *N) {
1687816870
if (!hasNoInfs(Options, FAdd))
1687916871
return SDValue();
1688016872

16873+
// Returns true if floating point contraction is allowed on the FMUL-SDValue
16874+
// `N`
16875+
auto isContractableFMUL = [this](const TargetOptions &Options, SDValue N) {
16876+
assert(N.getOpcode() == ISD::FMUL);
16877+
16878+
return Options.AllowFPOpFusion == FPOpFusion::Fast ||
16879+
DAG.getMachineFunction().hasUnsafeFPMath() ||
16880+
N->getFlags().hasAllowContract();
16881+
};
16882+
1688116883
// Floating-point multiply-add without intermediate rounding.
1688216884
bool HasFMA =
1688316885
isContractableFMUL(Options, SDValue(N, 0)) &&
@@ -16886,7 +16888,7 @@ SDValue DAGCombiner::visitFMULForFMADistributiveCombine(SDNode *N) {
1688616888

1688716889
// Floating-point multiply-add with intermediate rounding. This can result
1688816890
// in a less precise result due to the changed rounding order.
16889-
bool HasFMAD = Options.UnsafeFPMath &&
16891+
bool HasFMAD = DAG.getMachineFunction().hasUnsafeFPMath() &&
1689016892
(LegalOperations && TLI.isFMADLegal(DAG, N));
1689116893

1689216894
// No valid opcode, do not combine.
@@ -16971,6 +16973,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N) {
1697116973
SDValue N1 = N->getOperand(1);
1697216974
bool N0CFP = DAG.isConstantFPBuildVectorOrConstantFP(N0);
1697316975
bool N1CFP = DAG.isConstantFPBuildVectorOrConstantFP(N1);
16976+
bool UnsafeFPMath = DAG.getMachineFunction().hasUnsafeFPMath();
1697416977
EVT VT = N->getValueType(0);
1697516978
SDLoc DL(N);
1697616979
const TargetOptions &Options = DAG.getTarget().Options;
@@ -17052,7 +17055,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N) {
1705217055
// If 'unsafe math' or reassoc and nsz, fold lots of things.
1705317056
// TODO: break out portions of the transformations below for which Unsafe is
1705417057
// considered and which do not require both nsz and reassoc
17055-
if (((Options.UnsafeFPMath && Options.NoSignedZerosFPMath) ||
17058+
if (((UnsafeFPMath && Options.NoSignedZerosFPMath) ||
1705617059
(Flags.hasAllowReassociation() && Flags.hasNoSignedZeros())) &&
1705717060
AllowNewConst) {
1705817061
// fadd (fadd x, c1), c2 -> fadd x, c1 + c2
@@ -17190,6 +17193,7 @@ SDValue DAGCombiner::visitFSUB(SDNode *N) {
1719017193
const TargetOptions &Options = DAG.getTarget().Options;
1719117194
const SDNodeFlags Flags = N->getFlags();
1719217195
SelectionDAG::FlagInserter FlagsInserter(DAG, N);
17196+
bool UnsafeFPMath = DAG.getMachineFunction().hasUnsafeFPMath();
1719317197

1719417198
if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags))
1719517199
return R;
@@ -17239,7 +17243,7 @@ SDValue DAGCombiner::visitFSUB(SDNode *N) {
1723917243
}
1724017244
}
1724117245

17242-
if (((Options.UnsafeFPMath && Options.NoSignedZerosFPMath) ||
17246+
if (((UnsafeFPMath && Options.NoSignedZerosFPMath) ||
1724317247
(Flags.hasAllowReassociation() && Flags.hasNoSignedZeros())) &&
1724417248
N1.getOpcode() == ISD::FADD) {
1724517249
// X - (X + Y) -> -Y
@@ -17376,7 +17380,6 @@ SDValue DAGCombiner::visitFMUL(SDNode *N) {
1737617380
ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1, true);
1737717381
EVT VT = N->getValueType(0);
1737817382
SDLoc DL(N);
17379-
const TargetOptions &Options = DAG.getTarget().Options;
1738017383
const SDNodeFlags Flags = N->getFlags();
1738117384
SelectionDAG::FlagInserter FlagsInserter(DAG, N);
1738217385

@@ -17400,7 +17403,8 @@ SDValue DAGCombiner::visitFMUL(SDNode *N) {
1740017403
if (SDValue NewSel = foldBinOpIntoSelect(N))
1740117404
return NewSel;
1740217405

17403-
if (Options.UnsafeFPMath || Flags.hasAllowReassociation()) {
17406+
if (DAG.getMachineFunction().hasUnsafeFPMath() ||
17407+
Flags.hasAllowReassociation()) {
1740417408
// fmul (fmul X, C1), C2 -> fmul X, C1 * C2
1740517409
if (DAG.isConstantFPBuildVectorOrConstantFP(N1) &&
1740617410
N0.getOpcode() == ISD::FMUL) {
@@ -17526,10 +17530,10 @@ template <class MatchContextClass> SDValue DAGCombiner::visitFMA(SDNode *N) {
1752617530
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1752717531
EVT VT = N->getValueType(0);
1752817532
SDLoc DL(N);
17529-
const TargetOptions &Options = DAG.getTarget().Options;
1753017533
// FMA nodes have flags that propagate to the created nodes.
1753117534
SelectionDAG::FlagInserter FlagsInserter(DAG, N);
1753217535
MatchContextClass matcher(DAG, TLI, N);
17536+
bool UnsafeFPMath = DAG.getMachineFunction().hasUnsafeFPMath();
1753317537

1753417538
// Constant fold FMA.
1753517539
if (SDValue C =
@@ -17552,8 +17556,8 @@ template <class MatchContextClass> SDValue DAGCombiner::visitFMA(SDNode *N) {
1755217556
return matcher.getNode(ISD::FMA, DL, VT, NegN0, NegN1, N2);
1755317557
}
1755417558

17555-
// FIXME: use fast math flags instead of Options.UnsafeFPMath
17556-
if (Options.UnsafeFPMath) {
17559+
// FIXME: use fast math flags instead of MachineFunction::hasUnsafeFPMath()
17560+
if (UnsafeFPMath) {
1755717561
if (N0CFP && N0CFP->isZero())
1755817562
return N2;
1755917563
if (N1CFP && N1CFP->isZero())
@@ -17571,8 +17575,7 @@ template <class MatchContextClass> SDValue DAGCombiner::visitFMA(SDNode *N) {
1757117575
!DAG.isConstantFPBuildVectorOrConstantFP(N1))
1757217576
return matcher.getNode(ISD::FMA, DL, VT, N1, N0, N2);
1757317577

17574-
bool CanReassociate =
17575-
Options.UnsafeFPMath || N->getFlags().hasAllowReassociation();
17578+
bool CanReassociate = UnsafeFPMath || N->getFlags().hasAllowReassociation();
1757617579
if (CanReassociate) {
1757717580
// (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2)
1757817581
if (matcher.match(N2, ISD::FMUL) && N0 == N2.getOperand(0) &&
@@ -17667,7 +17670,7 @@ SDValue DAGCombiner::combineRepeatedFPDivisors(SDNode *N) {
1766717670
// TODO: Limit this transform based on optsize/minsize - it always creates at
1766817671
// least 1 extra instruction. But the perf win may be substantial enough
1766917672
// that only minsize should restrict this.
17670-
bool UnsafeMath = DAG.getTarget().Options.UnsafeFPMath;
17673+
bool UnsafeMath = DAG.getMachineFunction().hasUnsafeFPMath();
1767117674
const SDNodeFlags Flags = N->getFlags();
1767217675
if (LegalDAG || (!UnsafeMath && !Flags.hasAllowReciprocal()))
1767317676
return SDValue();
@@ -17744,6 +17747,7 @@ SDValue DAGCombiner::visitFDIV(SDNode *N) {
1774417747
const TargetOptions &Options = DAG.getTarget().Options;
1774517748
SDNodeFlags Flags = N->getFlags();
1774617749
SelectionDAG::FlagInserter FlagsInserter(DAG, N);
17750+
bool UnsafeFPMath = DAG.getMachineFunction().hasUnsafeFPMath();
1774717751

1774817752
if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags))
1774917753
return R;
@@ -17774,7 +17778,7 @@ SDValue DAGCombiner::visitFDIV(SDNode *N) {
1777417778
// isn't too nasty (eg NaN, denormal, ...).
1777517779
if (((st == APFloat::opOK && !Recip.isDenormal()) ||
1777617780
(st == APFloat::opInexact &&
17777-
(Options.UnsafeFPMath || Flags.hasAllowReciprocal()))) &&
17781+
(UnsafeFPMath || Flags.hasAllowReciprocal()))) &&
1777817782
(!LegalOperations ||
1777917783
// FIXME: custom lowering of ConstantFP might fail (see e.g. ARM
1778017784
// backend)... we should handle this gracefully after Legalize.
@@ -17785,7 +17789,7 @@ SDValue DAGCombiner::visitFDIV(SDNode *N) {
1778517789
DAG.getConstantFP(Recip, DL, VT));
1778617790
}
1778717791

17788-
if (Options.UnsafeFPMath || Flags.hasAllowReciprocal()) {
17792+
if (UnsafeFPMath || Flags.hasAllowReciprocal()) {
1778917793
// If this FDIV is part of a reciprocal square root, it may be folded
1779017794
// into a target-specific square root estimate instruction.
1779117795
if (N1.getOpcode() == ISD::FSQRT) {
@@ -17860,7 +17864,7 @@ SDValue DAGCombiner::visitFDIV(SDNode *N) {
1786017864

1786117865
// Fold X/Sqrt(X) -> Sqrt(X)
1786217866
if ((Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros()) &&
17863-
(Options.UnsafeFPMath || Flags.hasAllowReassociation()))
17867+
(UnsafeFPMath || Flags.hasAllowReassociation()))
1786417868
if (N1.getOpcode() == ISD::FSQRT && N0 == N1.getOperand(0))
1786517869
return N1;
1786617870

@@ -18356,7 +18360,7 @@ SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
1835618360
// single-step fp_round we want to fold to.
1835718361
// In other words, double rounding isn't the same as rounding.
1835818362
// Also, this is a value preserving truncation iff both fp_round's are.
18359-
if (DAG.getTarget().Options.UnsafeFPMath || N0IsTrunc)
18363+
if (DAG.getMachineFunction().hasUnsafeFPMath() || N0IsTrunc)
1836018364
return DAG.getNode(
1836118365
ISD::FP_ROUND, DL, VT, N0.getOperand(0),
1836218366
DAG.getIntPtrConstant(NIsTrunc && N0IsTrunc, DL, /*isTarget=*/true));

‎llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3643,7 +3643,7 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
36433643
break;
36443644
case ISD::FP_TO_FP16:
36453645
LLVM_DEBUG(dbgs() << "Legalizing FP_TO_FP16\n");
3646-
if (!TLI.useSoftFloat() && TM.Options.UnsafeFPMath) {
3646+
if (!TLI.useSoftFloat() && DAG.getMachineFunction().hasUnsafeFPMath()) {
36473647
SDValue Op = Node->getOperand(0);
36483648
MVT SVT = Op.getSimpleValueType();
36493649
if ((SVT == MVT::f64 || SVT == MVT::f80) &&

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11327,7 +11327,7 @@ SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
1132711327
AArch64CC::CondCode CC1, CC2;
1132811328
changeFPCCToAArch64CC(CC, CC1, CC2);
1132911329

11330-
if (DAG.getTarget().Options.UnsafeFPMath) {
11330+
if (DAG.getMachineFunction().hasUnsafeFPMath()) {
1133111331
// Transform "a == 0.0 ? 0.0 : x" to "a == 0.0 ? a : x" and
1133211332
// "a != 0.0 ? x : 0.0" to "a != 0.0 ? x : a" to avoid materializing 0.0.
1133311333
ConstantFPSDNode *RHSVal = dyn_cast<ConstantFPSDNode>(RHS);

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6351,7 +6351,7 @@ static bool isCombineInstrCandidateFP(const MachineInstr &Inst) {
63516351
TargetOptions Options = Inst.getParent()->getParent()->getTarget().Options;
63526352
// We can fuse FADD/FSUB with FMUL, if fusion is either allowed globally by
63536353
// the target options or if FADD/FSUB has the contract fast-math flag.
6354-
return Options.UnsafeFPMath ||
6354+
return Inst.getParent()->getParent()->hasUnsafeFPMath() ||
63556355
Options.AllowFPOpFusion == FPOpFusion::Fast ||
63566356
Inst.getFlag(MachineInstr::FmContract);
63576357
return true;
@@ -6457,7 +6457,7 @@ bool AArch64InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst,
64576457
case AArch64::FMUL_ZZZ_H:
64586458
case AArch64::FMUL_ZZZ_S:
64596459
case AArch64::FMUL_ZZZ_D:
6460-
return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath ||
6460+
return Inst.getParent()->getParent()->hasUnsafeFPMath() ||
64616461
(Inst.getFlag(MachineInstr::MIFlag::FmReassoc) &&
64626462
Inst.getFlag(MachineInstr::MIFlag::FmNsz));
64636463

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2623,7 +2623,7 @@ bool AMDGPUTargetLowering::allowApproxFunc(const SelectionDAG &DAG,
26232623
if (Flags.hasApproximateFuncs())
26242624
return true;
26252625
auto &Options = DAG.getTarget().Options;
2626-
return Options.UnsafeFPMath || Options.ApproxFuncFPMath;
2626+
return DAG.getMachineFunction().hasUnsafeFPMath() || Options.ApproxFuncFPMath;
26272627
}
26282628

26292629
bool AMDGPUTargetLowering::needsDenormHandlingF32(const SelectionDAG &DAG,
@@ -2746,7 +2746,7 @@ SDValue AMDGPUTargetLowering::LowerFLOGCommon(SDValue Op,
27462746

27472747
const auto &Options = getTargetMachine().Options;
27482748
if (VT == MVT::f16 || Flags.hasApproximateFuncs() ||
2749-
Options.ApproxFuncFPMath || Options.UnsafeFPMath) {
2749+
Options.ApproxFuncFPMath || DAG.getMachineFunction().hasUnsafeFPMath()) {
27502750

27512751
if (VT == MVT::f16 && !Subtarget->has16BitInsts()) {
27522752
// Log and multiply in f32 is good enough for f16.
@@ -3573,7 +3573,7 @@ SDValue AMDGPUTargetLowering::LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) con
35733573
if (N0.getValueType() == MVT::f32)
35743574
return DAG.getNode(AMDGPUISD::FP_TO_FP16, DL, Op.getValueType(), N0);
35753575

3576-
if (getTargetMachine().Options.UnsafeFPMath) {
3576+
if (DAG.getMachineFunction().hasUnsafeFPMath()) {
35773577
// There is a generic expand for FP_TO_FP16 with unsafe fast math.
35783578
return SDValue();
35793579
}

‎llvm/lib/Target/AMDGPU/AMDGPUInstructions.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -94,7 +94,7 @@ def FP64Denormals : Predicate<"MF->getInfo<SIMachineFunctionInfo>()->getMode().F
9494
def NoFP16Denormals : Predicate<"MF->getInfo<SIMachineFunctionInfo>()->getMode().FP64FP16Denormals == DenormalMode::getPreserveSign()">;
9595
def NoFP32Denormals : Predicate<"MF->getInfo<SIMachineFunctionInfo>()->getMode().FP32Denormals == DenormalMode::getPreserveSign()">;
9696
def NoFP64Denormals : Predicate<"MF->getInfo<SIMachineFunctionInfo>()->getMode().FP64FP16Denormals == DenormalMode::getPreserveSign()">;
97-
def UnsafeFPMath : Predicate<"TM.Options.UnsafeFPMath">;
97+
def UnsafeFPMath : Predicate<"MF->hasUnsafeFPMath()">;
9898
}
9999

100100
def FMA : Predicate<"Subtarget->hasFMA()">;

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -3270,7 +3270,7 @@ static bool allowApproxFunc(const MachineFunction &MF, unsigned Flags) {
32703270
if (Flags & MachineInstr::FmAfn)
32713271
return true;
32723272
const auto &Options = MF.getTarget().Options;
3273-
return Options.UnsafeFPMath || Options.ApproxFuncFPMath;
3273+
return MF.hasUnsafeFPMath() || Options.ApproxFuncFPMath;
32743274
}
32753275

32763276
static bool needsDenormHandlingF32(const MachineFunction &MF, Register Src,
@@ -3376,7 +3376,7 @@ bool AMDGPULegalizerInfo::legalizeFlogCommon(MachineInstr &MI,
33763376
static_cast<const AMDGPUTargetMachine &>(MF.getTarget());
33773377

33783378
if (Ty == F16 || MI.getFlag(MachineInstr::FmAfn) ||
3379-
TM.Options.ApproxFuncFPMath || TM.Options.UnsafeFPMath) {
3379+
TM.Options.ApproxFuncFPMath || MF.hasUnsafeFPMath()) {
33803380
if (Ty == F16 && !ST.has16BitInsts()) {
33813381
Register LogVal = MRI.createGenericVirtualRegister(F32);
33823382
auto PromoteSrc = B.buildFPExt(F32, X);
@@ -4802,8 +4802,8 @@ bool AMDGPULegalizerInfo::legalizeFastUnsafeFDIV(MachineInstr &MI,
48024802
LLT ResTy = MRI.getType(Res);
48034803

48044804
const MachineFunction &MF = B.getMF();
4805-
bool AllowInaccurateRcp = MI.getFlag(MachineInstr::FmAfn) ||
4806-
MF.getTarget().Options.UnsafeFPMath;
4805+
bool AllowInaccurateRcp =
4806+
MI.getFlag(MachineInstr::FmAfn) || MF.hasUnsafeFPMath();
48074807

48084808
if (const auto *CLHS = getConstantFPVRegVal(LHS, MRI)) {
48094809
if (!AllowInaccurateRcp && ResTy != LLT::scalar(16))
@@ -4864,8 +4864,8 @@ bool AMDGPULegalizerInfo::legalizeFastUnsafeFDIV64(MachineInstr &MI,
48644864
LLT ResTy = MRI.getType(Res);
48654865

48664866
const MachineFunction &MF = B.getMF();
4867-
bool AllowInaccurateRcp = MF.getTarget().Options.UnsafeFPMath ||
4868-
MI.getFlag(MachineInstr::FmAfn);
4867+
bool AllowInaccurateRcp =
4868+
MF.hasUnsafeFPMath() || MI.getFlag(MachineInstr::FmAfn);
48694869

48704870
if (!AllowInaccurateRcp)
48714871
return false;

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