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AMDGPU: Add baseline tests for bitcast + readlane intrinsics (#128493)
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‎llvm/test/Transforms/InstCombine/AMDGPU/bitcast-fold-lane-ops.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -passes=instcombine -S < %s | FileCheck %s
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define i32 @test_bitcast_f32_to_i32_readfirstlane(float %val) {
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; CHECK-LABEL: define i32 @test_bitcast_f32_to_i32_readfirstlane(
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; CHECK-SAME: float [[VAL:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[BITCAST:%.*]] = bitcast float [[VAL]] to i32
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; CHECK-NEXT: [[RESULT:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[BITCAST]])
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; CHECK-NEXT: ret i32 [[RESULT]]
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;
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%bitcast = bitcast float %val to i32
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%result = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %bitcast)
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ret i32 %result
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}
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define i32 @test_bitcast_f32_to_i32_readfirstlane_multi_use_store(float %val, ptr %use.ptr) {
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; CHECK-LABEL: define i32 @test_bitcast_f32_to_i32_readfirstlane_multi_use_store(
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; CHECK-SAME: float [[VAL:%.*]], ptr [[USE_PTR:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[BITCAST:%.*]] = bitcast float [[VAL]] to i32
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; CHECK-NEXT: store float [[VAL]], ptr [[USE_PTR]], align 4
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; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[BITCAST]])
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; CHECK-NEXT: ret i32 [[TMP1]]
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;
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%bitcast = bitcast float %val to i32
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store i32 %bitcast, ptr %use.ptr
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%result = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %bitcast)
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ret i32 %result
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}
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declare void @use.i32(i32)
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define i32 @test_bitcast_f32_to_i32_readfirstlane_multi_use_call(float %val) {
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; CHECK-LABEL: define i32 @test_bitcast_f32_to_i32_readfirstlane_multi_use_call(
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; CHECK-SAME: float [[VAL:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[BITCAST:%.*]] = bitcast float [[VAL]] to i32
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; CHECK-NEXT: call void @use.i32(i32 [[BITCAST]])
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; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[BITCAST]])
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; CHECK-NEXT: ret i32 [[TMP1]]
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;
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%bitcast = bitcast float %val to i32
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call void @use.i32(i32 %bitcast)
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%result = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %bitcast)
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ret i32 %result
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}
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define float @test_bitcast_f32_to_i32_readfirstlane_bitcast(float %val) {
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; CHECK-LABEL: define float @test_bitcast_f32_to_i32_readfirstlane_bitcast(
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; CHECK-SAME: float [[VAL:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[BITCAST:%.*]] = bitcast float [[VAL]] to i32
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; CHECK-NEXT: [[CALL:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[BITCAST]])
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; CHECK-NEXT: [[RESULT:%.*]] = bitcast i32 [[CALL]] to float
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; CHECK-NEXT: ret float [[RESULT]]
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;
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%bitcast = bitcast float %val to i32
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%call = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %bitcast)
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%result = bitcast i32 %call to float
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ret float %result
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}
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define i32 @test_bitcast_v2f16_to_i32_readfirstlane(<2 x half> %val) {
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; CHECK-LABEL: define i32 @test_bitcast_v2f16_to_i32_readfirstlane(
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; CHECK-SAME: <2 x half> [[VAL:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[BITCAST:%.*]] = bitcast <2 x half> [[VAL]] to i32
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; CHECK-NEXT: [[RESULT:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[BITCAST]])
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; CHECK-NEXT: ret i32 [[RESULT]]
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;
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%bitcast = bitcast <2 x half> %val to i32
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%result = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %bitcast)
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ret i32 %result
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}
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define i32 @test_bitcast_v2bf16_to_i32_readfirstlane(<2 x bfloat> %val) {
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; CHECK-LABEL: define i32 @test_bitcast_v2bf16_to_i32_readfirstlane(
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; CHECK-SAME: <2 x bfloat> [[VAL:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[BITCAST:%.*]] = bitcast <2 x bfloat> [[VAL]] to i32
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; CHECK-NEXT: [[RESULT:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[BITCAST]])
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; CHECK-NEXT: ret i32 [[RESULT]]
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;
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%bitcast = bitcast <2 x bfloat> %val to i32
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%result = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %bitcast)
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ret i32 %result
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}
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define i64 @test_bitcast_f64_to_i64_readfirstlane(double %val) {
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; CHECK-LABEL: define i64 @test_bitcast_f64_to_i64_readfirstlane(
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; CHECK-SAME: double [[VAL:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[BITCAST:%.*]] = bitcast double [[VAL]] to i64
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; CHECK-NEXT: [[RESULT:%.*]] = call i64 @llvm.amdgcn.readfirstlane.i64(i64 [[BITCAST]])
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; CHECK-NEXT: ret i64 [[RESULT]]
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;
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%bitcast = bitcast double %val to i64
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%result = call i64 @llvm.amdgcn.readfirstlane.i64(i64 %bitcast)
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ret i64 %result
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}
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define <2 x i32> @test_bitcast_f64_to_v2i32_readfirstlane(double %val) {
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; CHECK-LABEL: define <2 x i32> @test_bitcast_f64_to_v2i32_readfirstlane(
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; CHECK-SAME: double [[VAL:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[BITCAST:%.*]] = bitcast double [[VAL]] to <2 x i32>
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; CHECK-NEXT: [[RESULT:%.*]] = call <2 x i32> @llvm.amdgcn.readfirstlane.v2i32(<2 x i32> [[BITCAST]])
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; CHECK-NEXT: ret <2 x i32> [[RESULT]]
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;
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%bitcast = bitcast double %val to <2 x i32>
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%result = call <2 x i32> @llvm.amdgcn.readfirstlane.v2i32(<2 x i32> %bitcast)
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ret <2 x i32> %result
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}
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define i64 @test_bitcast_v4i16_to_i64_readfirstlane(<4 x i16> %val) {
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; CHECK-LABEL: define i64 @test_bitcast_v4i16_to_i64_readfirstlane(
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; CHECK-SAME: <4 x i16> [[VAL:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[BITCAST:%.*]] = bitcast <4 x i16> [[VAL]] to i64
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; CHECK-NEXT: [[RESULT:%.*]] = call i64 @llvm.amdgcn.readfirstlane.i64(i64 [[BITCAST]])
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; CHECK-NEXT: ret i64 [[RESULT]]
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;
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%bitcast = bitcast <4 x i16> %val to i64
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%result = call i64 @llvm.amdgcn.readfirstlane.i64(i64 %bitcast)
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ret i64 %result
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}
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define i32 @test_bitcast_v4i8_to_i32_readfirstlane(<4 x i8> %val) {
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; CHECK-LABEL: define i32 @test_bitcast_v4i8_to_i32_readfirstlane(
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; CHECK-SAME: <4 x i8> [[VAL:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[BITCAST:%.*]] = bitcast <4 x i8> [[VAL]] to i32
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; CHECK-NEXT: [[RESULT:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[BITCAST]])
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; CHECK-NEXT: ret i32 [[RESULT]]
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;
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%bitcast = bitcast <4 x i8> %val to i32
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%result = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %bitcast)
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ret i32 %result
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}
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define i32 @test_bitcast_v8i4_to_i32_readfirstlane(<8 x i4> %val) {
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; CHECK-LABEL: define i32 @test_bitcast_v8i4_to_i32_readfirstlane(
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; CHECK-SAME: <8 x i4> [[VAL:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[BITCAST:%.*]] = bitcast <8 x i4> [[VAL]] to i32
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; CHECK-NEXT: [[RESULT:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[BITCAST]])
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; CHECK-NEXT: ret i32 [[RESULT]]
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;
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%bitcast = bitcast <8 x i4> %val to i32
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%result = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %bitcast)
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ret i32 %result
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}
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define float @test_bitcast_i32_to_f32_readfirstlane(i32 %val) {
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; CHECK-LABEL: define float @test_bitcast_i32_to_f32_readfirstlane(
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; CHECK-SAME: i32 [[VAL:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[BITCAST:%.*]] = bitcast i32 [[VAL]] to float
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; CHECK-NEXT: [[RESULT:%.*]] = call float @llvm.amdgcn.readfirstlane.f32(float [[BITCAST]])
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; CHECK-NEXT: ret float [[RESULT]]
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;
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%bitcast = bitcast i32 %val to float
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%result = call float @llvm.amdgcn.readfirstlane.f32(float %bitcast)
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ret float %result
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}
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define i16 @test_bitcast_f16_to_i16_readfirstlane(half %val) {
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; CHECK-LABEL: define i16 @test_bitcast_f16_to_i16_readfirstlane(
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; CHECK-SAME: half [[VAL:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[BITCAST:%.*]] = bitcast half [[VAL]] to i16
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; CHECK-NEXT: [[RESULT:%.*]] = call i16 @llvm.amdgcn.readfirstlane.i16(i16 [[BITCAST]])
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; CHECK-NEXT: ret i16 [[RESULT]]
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;
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%bitcast = bitcast half %val to i16
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%result = call i16 @llvm.amdgcn.readfirstlane.i16(i16 %bitcast)
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ret i16 %result
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}
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define i16 @test_bitcast_v2i8_to_i16_readfirstlane(<2 x i8> %val) {
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; CHECK-LABEL: define i16 @test_bitcast_v2i8_to_i16_readfirstlane(
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; CHECK-SAME: <2 x i8> [[VAL:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[BITCAST:%.*]] = bitcast <2 x i8> [[VAL]] to i16
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; CHECK-NEXT: [[RESULT:%.*]] = call i16 @llvm.amdgcn.readfirstlane.i16(i16 [[BITCAST]])
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; CHECK-NEXT: ret i16 [[RESULT]]
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;
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%bitcast = bitcast <2 x i8> %val to i16
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%result = call i16 @llvm.amdgcn.readfirstlane.i16(i16 %bitcast)
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ret i16 %result
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}
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define <16 x i32> @test_bitcast_v16f32_to_v16i32_readfirstlane(<16 x float> %val) {
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; CHECK-LABEL: define <16 x i32> @test_bitcast_v16f32_to_v16i32_readfirstlane(
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; CHECK-SAME: <16 x float> [[VAL:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[BITCAST:%.*]] = bitcast <16 x float> [[VAL]] to <16 x i32>
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; CHECK-NEXT: [[TMP1:%.*]] = call <16 x i32> @llvm.amdgcn.readfirstlane.v16i32(<16 x i32> [[BITCAST]])
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; CHECK-NEXT: ret <16 x i32> [[TMP1]]
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;
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%bitcast = bitcast <16 x float> %val to <16 x i32>
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%result = call <16 x i32> @llvm.amdgcn.readfirstlane.v16i32(<16 x i32> %bitcast)
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ret <16 x i32> %result
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}
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define <8 x i64> @test_bitcast_v16f32_to_v8i64_readfirstlane(<16 x float> %val) {
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; CHECK-LABEL: define <8 x i64> @test_bitcast_v16f32_to_v8i64_readfirstlane(
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; CHECK-SAME: <16 x float> [[VAL:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[BITCAST:%.*]] = bitcast <16 x float> [[VAL]] to <8 x i64>
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; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i64> @llvm.amdgcn.readfirstlane.v8i64(<8 x i64> [[BITCAST]])
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; CHECK-NEXT: ret <8 x i64> [[TMP1]]
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;
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%bitcast = bitcast <16 x float> %val to <8 x i64>
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%result = call <8 x i64> @llvm.amdgcn.readfirstlane.v8i64(<8 x i64> %bitcast)
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ret <8 x i64> %result
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}
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define i32 @test_bitcast_f32_to_i32_readlane(float %val, i32 inreg %lane.index) {
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; CHECK-LABEL: define i32 @test_bitcast_f32_to_i32_readlane(
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; CHECK-SAME: float [[VAL:%.*]], i32 inreg [[LANE_INDEX:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[BITCAST:%.*]] = bitcast float [[VAL]] to i32
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; CHECK-NEXT: [[RESULT:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[BITCAST]], i32 [[LANE_INDEX]])
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; CHECK-NEXT: ret i32 [[RESULT]]
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;
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%bitcast = bitcast float %val to i32
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%result = call i32 @llvm.amdgcn.readlane.i32(i32 %bitcast, i32 %lane.index)
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ret i32 %result
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}
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define i32 @test_bitcast_f32_to_i32_writelane_samesourcetype(float %val0, i32 inreg %lane.index, float %val1) {
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; CHECK-LABEL: define i32 @test_bitcast_f32_to_i32_writelane_samesourcetype(
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; CHECK-SAME: float [[VAL0:%.*]], i32 inreg [[LANE_INDEX:%.*]], float [[VAL1:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[BITCAST0:%.*]] = bitcast float [[VAL0]] to i32
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; CHECK-NEXT: [[BITCAST1:%.*]] = bitcast float [[VAL1]] to i32
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; CHECK-NEXT: [[RESULT:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[BITCAST0]], i32 [[LANE_INDEX]], i32 [[BITCAST1]])
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; CHECK-NEXT: ret i32 [[RESULT]]
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;
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%bitcast0 = bitcast float %val0 to i32
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%bitcast1 = bitcast float %val1 to i32
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%result = call i32 @llvm.amdgcn.writelane.i32(i32 %bitcast0, i32 %lane.index, i32 %bitcast1)
228+
ret i32 %result
229+
}
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define i32 @test_bitcast_f32_to_i32_writelane_diffsourcetype(float %val0, i32 inreg %lane.index, <2 x half> %val1) {
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; CHECK-LABEL: define i32 @test_bitcast_f32_to_i32_writelane_diffsourcetype(
233+
; CHECK-SAME: float [[VAL0:%.*]], i32 inreg [[LANE_INDEX:%.*]], <2 x half> [[VAL1:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[BITCAST0:%.*]] = bitcast float [[VAL0]] to i32
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; CHECK-NEXT: [[BITCAST1:%.*]] = bitcast <2 x half> [[VAL1]] to i32
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; CHECK-NEXT: [[RESULT:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[BITCAST0]], i32 [[LANE_INDEX]], i32 [[BITCAST1]])
237+
; CHECK-NEXT: ret i32 [[RESULT]]
238+
;
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%bitcast0 = bitcast float %val0 to i32
240+
%bitcast1 = bitcast <2 x half> %val1 to i32
241+
%result = call i32 @llvm.amdgcn.writelane.i32(i32 %bitcast0, i32 %lane.index, i32 %bitcast1)
242+
ret i32 %result
243+
}
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define i32 @test_bitcast_update_dpp_f32_to_i32(float %val0, float %val1) {
246+
; CHECK-LABEL: define i32 @test_bitcast_update_dpp_f32_to_i32(
247+
; CHECK-SAME: float [[VAL0:%.*]], float [[VAL1:%.*]]) #[[ATTR0]] {
248+
; CHECK-NEXT: [[BITCAST0:%.*]] = bitcast float [[VAL0]] to i32
249+
; CHECK-NEXT: [[BITCAST1:%.*]] = bitcast float [[VAL1]] to i32
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; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 [[BITCAST0]], i32 [[BITCAST1]], i32 1, i32 1, i32 1, i1 false)
251+
; CHECK-NEXT: ret i32 [[TMP0]]
252+
;
253+
%bitcast0 = bitcast float %val0 to i32
254+
%bitcast1 = bitcast float %val1 to i32
255+
%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 %bitcast0, i32 %bitcast1, i32 1, i32 1, i32 1, i1 false)
256+
ret i32 %dpp
257+
}
258+
259+
define i32 @test_bitcast_update_dpp_f32_to_i32_convergencetoken(float %val0, float %val1) convergent {
260+
; CHECK-LABEL: define i32 @test_bitcast_update_dpp_f32_to_i32_convergencetoken(
261+
; CHECK-SAME: float [[VAL0:%.*]], float [[VAL1:%.*]]) #[[ATTR1:[0-9]+]] {
262+
; CHECK-NEXT: [[T:%.*]] = call token @llvm.experimental.convergence.entry()
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; CHECK-NEXT: [[BITCAST0:%.*]] = bitcast float [[VAL0]] to i32
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; CHECK-NEXT: [[BITCAST1:%.*]] = bitcast float [[VAL1]] to i32
265+
; CHECK-NEXT: [[DPP:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 [[BITCAST0]], i32 [[BITCAST1]], i32 1, i32 1, i32 1, i1 false) [ "convergencectrl"(token [[T]]) ]
266+
; CHECK-NEXT: ret i32 [[DPP]]
267+
;
268+
%t = call token @llvm.experimental.convergence.entry()
269+
%bitcast0 = bitcast float %val0 to i32
270+
%bitcast1 = bitcast float %val1 to i32
271+
%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 %bitcast0, i32 %bitcast1, i32 1, i32 1, i32 1, i1 false) [ "convergencectrl"(token %t) ]
272+
ret i32 %dpp
273+
}
274+
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define i32 @test_bitcast_update_dpp_sources_different_type(float %val0, <2 x half> %val1) {
276+
; CHECK-LABEL: define i32 @test_bitcast_update_dpp_sources_different_type(
277+
; CHECK-SAME: float [[VAL0:%.*]], <2 x half> [[VAL1:%.*]]) #[[ATTR0]] {
278+
; CHECK-NEXT: [[BITCAST0:%.*]] = bitcast float [[VAL0]] to i32
279+
; CHECK-NEXT: [[BITCAST1:%.*]] = bitcast <2 x half> [[VAL1]] to i32
280+
; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.update.dpp.i32(i32 [[BITCAST0]], i32 [[BITCAST1]], i32 1, i32 1, i32 1, i1 false)
281+
; CHECK-NEXT: ret i32 [[TMP0]]
282+
;
283+
%bitcast0 = bitcast float %val0 to i32
284+
%bitcast1 = bitcast <2 x half> %val1 to i32
285+
%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 %bitcast0, i32 %bitcast1, i32 1, i32 1, i32 1, i1 false)
286+
ret i32 %dpp
287+
}
288+
289+
define i32 @test_bitcast_f32_to_i32_readfirstlane_convergencetoken(float %val) convergent {
290+
; CHECK-LABEL: define i32 @test_bitcast_f32_to_i32_readfirstlane_convergencetoken(
291+
; CHECK-SAME: float [[VAL:%.*]]) #[[ATTR1]] {
292+
; CHECK-NEXT: [[T:%.*]] = call token @llvm.experimental.convergence.entry()
293+
; CHECK-NEXT: [[BITCAST:%.*]] = bitcast float [[VAL]] to i32
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; CHECK-NEXT: [[RESULT:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[BITCAST]]) [ "convergencectrl"(token [[T]]) ]
295+
; CHECK-NEXT: ret i32 [[RESULT]]
296+
;
297+
%t = call token @llvm.experimental.convergence.entry()
298+
%bitcast = bitcast float %val to i32
299+
%result = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %bitcast) [ "convergencectrl"(token %t) ]
300+
ret i32 %result
301+
}
302+
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define i32 @test_bitcast_f32_to_i32_readlane_convergencetoken(float %val, i32 inreg %lane.index) convergent {
304+
; CHECK-LABEL: define i32 @test_bitcast_f32_to_i32_readlane_convergencetoken(
305+
; CHECK-SAME: float [[VAL:%.*]], i32 inreg [[LANE_INDEX:%.*]]) #[[ATTR1]] {
306+
; CHECK-NEXT: [[T:%.*]] = call token @llvm.experimental.convergence.entry()
307+
; CHECK-NEXT: [[BITCAST:%.*]] = bitcast float [[VAL]] to i32
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; CHECK-NEXT: [[RESULT:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[BITCAST]], i32 [[LANE_INDEX]]) [ "convergencectrl"(token [[T]]) ]
309+
; CHECK-NEXT: ret i32 [[RESULT]]
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;
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%t = call token @llvm.experimental.convergence.entry()
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%bitcast = bitcast float %val to i32
313+
%result = call i32 @llvm.amdgcn.readlane.i32(i32 %bitcast, i32 %lane.index) [ "convergencectrl"(token %t) ]
314+
ret i32 %result
315+
}

‎llvm/test/Transforms/InstCombine/AMDGPU/permlane64.ll

Lines changed: 26 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,32 @@ define i32 @test_constant() {
66
; CHECK-LABEL: @test_constant(
77
; CHECK-NEXT: ret i32 99
88
;
9-
%call = call i32 @llvm.amdgcn.permlane64(i32 99)
9+
%call = call i32 @llvm.amdgcn.permlane64.i32(i32 99)
1010
ret i32 %call
1111
}
1212

13-
declare i32 @llvm.amdgcn.permlane64(i32)
13+
define i32 @test_bitcast_f32_to_i32_permlane64(float %val) {
14+
; CHECK-LABEL: @test_bitcast_f32_to_i32_permlane64(
15+
; CHECK-NEXT: [[BITCAST:%.*]] = bitcast float [[VAL:%.*]] to i32
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; CHECK-NEXT: [[RESULT:%.*]] = call i32 @llvm.amdgcn.permlane64.i32(i32 [[BITCAST]])
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; CHECK-NEXT: ret i32 [[RESULT]]
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;
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%bitcast = bitcast float %val to i32
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%result = call i32 @llvm.amdgcn.permlane64.i32(i32 %bitcast)
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ret i32 %result
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}
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define i32 @test_bitcast_f32_to_i32_permlane64_convergencetokenn(float %val) convergent {
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; CHECK-LABEL: @test_bitcast_f32_to_i32_permlane64_convergencetokenn(
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; CHECK-NEXT: [[T:%.*]] = call token @llvm.experimental.convergence.entry()
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; CHECK-NEXT: [[BITCAST:%.*]] = bitcast float [[VAL:%.*]] to i32
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; CHECK-NEXT: [[RESULT:%.*]] = call i32 @llvm.amdgcn.permlane64.i32(i32 [[BITCAST]]) [ "convergencectrl"(token [[T]]) ]
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; CHECK-NEXT: ret i32 [[RESULT]]
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;
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%t = call token @llvm.experimental.convergence.entry()
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%bitcast = bitcast float %val to i32
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%result = call i32 @llvm.amdgcn.permlane64.i32(i32 %bitcast) [ "convergencectrl"(token %t) ]
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ret i32 %result
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}
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declare i32 @llvm.amdgcn.permlane64.i32(i32)

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