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mtsokolmtsokol
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Further improvements
1 parent b62284a commit 2af2004

11 files changed

+336
-330
lines changed

‎llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Lines changed: 16 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -455,7 +455,8 @@ bool CombinerHelper::matchCombineShuffleConcat(
455455
return false;
456456
}
457457
if (!isLegalOrBeforeLegalizer(
458-
{TargetOpcode::G_IMPLICIT_DEF, {ConcatSrcTy}}))
458+
{TargetOpcode::G_IMPLICIT_DEF, {ConcatSrcTy}}) ||
459+
!isLegalOrBeforeLegalizer({TargetOpcode::G_POISON, {ConcatSrcTy}}))
459460
return false;
460461
Ops.push_back(0);
461462
} else if (Mask[i] % ConcatSrcNumElt == 0) {
@@ -2733,7 +2734,8 @@ void CombinerHelper::applyCombineTruncOfShift(
27332734
bool CombinerHelper::matchAnyExplicitUseIsUndef(MachineInstr &MI) const {
27342735
return any_of(MI.explicit_uses(), [this](const MachineOperand &MO) {
27352736
return MO.isReg() &&
2736-
getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MO.getReg(), MRI);
2737+
(getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MO.getReg(), MRI) ||
2738+
getOpcodeDef(TargetOpcode::G_POISON, MO.getReg(), MRI));
27372739
});
27382740
}
27392741

@@ -2746,7 +2748,8 @@ bool CombinerHelper::matchAnyExplicitUseIsPoison(MachineInstr &MI) const {
27462748
bool CombinerHelper::matchAllExplicitUsesAreUndef(MachineInstr &MI) const {
27472749
return all_of(MI.explicit_uses(), [this](const MachineOperand &MO) {
27482750
return !MO.isReg() ||
2749-
getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MO.getReg(), MRI);
2751+
getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MO.getReg(), MRI) ||
2752+
getOpcodeDef(TargetOpcode::G_POISON, MO.getReg(), MRI);
27502753
});
27512754
}
27522755

@@ -2766,6 +2769,8 @@ bool CombinerHelper::matchUndefShuffleVectorMask(MachineInstr &MI) const {
27662769
bool CombinerHelper::matchUndefStore(MachineInstr &MI) const {
27672770
assert(MI.getOpcode() == TargetOpcode::G_STORE);
27682771
return getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MI.getOperand(0).getReg(),
2772+
MRI) ||
2773+
getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MI.getOperand(0).getReg(),
27692774
MRI);
27702775
}
27712776

@@ -2777,6 +2782,8 @@ bool CombinerHelper::matchPoisonStore(MachineInstr &MI) const {
27772782
bool CombinerHelper::matchUndefSelectCmp(MachineInstr &MI) const {
27782783
assert(MI.getOpcode() == TargetOpcode::G_SELECT);
27792784
return getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MI.getOperand(1).getReg(),
2785+
MRI) ||
2786+
getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MI.getOperand(1).getReg(),
27802787
MRI);
27812788
}
27822789

@@ -3010,7 +3017,8 @@ bool CombinerHelper::matchOperandIsUndef(MachineInstr &MI,
30103017
unsigned OpIdx) const {
30113018
MachineOperand &MO = MI.getOperand(OpIdx);
30123019
return MO.isReg() &&
3013-
getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MO.getReg(), MRI);
3020+
(getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MO.getReg(), MRI) ||
3021+
getOpcodeDef(TargetOpcode::G_POISON, MO.getReg(), MRI));
30143022
}
30153023

30163024
bool CombinerHelper::matchOperandIsPoison(MachineInstr &MI,
@@ -7960,10 +7968,12 @@ bool CombinerHelper::matchShuffleDisjointMask(MachineInstr &MI,
79607968
auto &Shuffle = cast<GShuffleVector>(MI);
79617969
// If any of the two inputs is already undef, don't check the mask again to
79627970
// prevent infinite loop
7963-
if (getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, Shuffle.getSrc1Reg(), MRI))
7971+
if (getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, Shuffle.getSrc1Reg(), MRI) ||
7972+
getOpcodeDef(TargetOpcode::G_POISON, Shuffle.getSrc1Reg(), MRI))
79647973
return false;
79657974

7966-
if (getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, Shuffle.getSrc2Reg(), MRI))
7975+
if (getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, Shuffle.getSrc2Reg(), MRI) ||
7976+
getOpcodeDef(TargetOpcode::G_POISON, Shuffle.getSrc2Reg(), MRI))
79677977
return false;
79687978

79697979
const LLT DstTy = MRI.getType(Shuffle.getReg(0));

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -8454,16 +8454,16 @@ LegalizerHelper::lowerVECTOR_COMPRESS(llvm::MachineInstr &MI) {
84548454

84558455
auto OutPos = MIRBuilder.buildConstant(IdxTy, 0);
84568456

8457-
bool HasPassthru =
8458-
MRI.getVRegDef(Passthru)->getOpcode() != TargetOpcode::G_IMPLICIT_DEF &&
8459-
MRI.getVRegDef(Passthru)->getOpcode() != TargetOpcode::G_POISON;
8457+
auto *PassthruMI = MRI.getVRegDef(Passthru);
8458+
bool HasPassthru = PassthruMI->getOpcode() != TargetOpcode::G_IMPLICIT_DEF &&
8459+
PassthruMI->getOpcode() != TargetOpcode::G_POISON;
84608460

84618461
if (HasPassthru)
84628462
MIRBuilder.buildStore(Passthru, StackPtr, PtrInfo, VecAlign);
84638463

84648464
Register LastWriteVal;
84658465
std::optional<APInt> PassthruSplatVal =
8466-
isConstantOrConstantSplatVector(*MRI.getVRegDef(Passthru), MRI);
8466+
isConstantOrConstantSplatVector(*PassthruMI, MRI);
84678467

84688468
if (PassthruSplatVal.has_value()) {
84698469
LastWriteVal =

‎llvm/lib/Target/AArch64/AArch64Combine.td

Lines changed: 15 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -131,23 +131,19 @@ def ext: GICombineRule <
131131
(apply [{ applyEXT(*${root}, ${matchinfo}); }])
132132
>;
133133

134-
def fullrev: GICombineRule <
135-
(defs root:$root, shuffle_matchdata:$matchinfo),
136-
(match (G_IMPLICIT_DEF $src2),
137-
(G_SHUFFLE_VECTOR $src, $src1, $src2, $mask):$root,
138-
[{ return ShuffleVectorInst::isReverseMask(${mask}.getShuffleMask(),
139-
${mask}.getShuffleMask().size()); }]),
140-
(apply [{ applyFullRev(*${root}, MRI); }])
141-
>;
142-
143-
def fullrevpoison: GICombineRule <
144-
(defs root:$root, shuffle_matchdata:$matchinfo),
145-
(match (G_POISON $src2),
146-
(G_SHUFFLE_VECTOR $src, $src1, $src2, $mask):$root,
147-
[{ return ShuffleVectorInst::isReverseMask(${mask}.getShuffleMask(),
134+
def undef_or_poison_op
135+
: GICombinePatFrag<(outs root:$src2), (ins),
136+
!foreach(op, [G_IMPLICIT_DEF, G_POISON],
137+
(pattern(op $src2)))>;
138+
139+
def fullrev
140+
: GICombineRule<
141+
(defs root:$root, shuffle_matchdata:$matchinfo),
142+
(match(undef_or_poison_op $src2),
143+
(G_SHUFFLE_VECTOR $src, $src1, $src2, $mask):$root,
144+
[{ return ShuffleVectorInst::isReverseMask(${mask}.getShuffleMask(),
148145
${mask}.getShuffleMask().size()); }]),
149-
(apply [{ applyFullRev(*${root}, MRI); }])
150-
>;
146+
(apply [{ applyFullRev(*${root}, MRI); }])>;
151147

152148
def insertelt_nonconst: GICombineRule <
153149
(defs root:$root, shuffle_matchdata:$matchinfo),
@@ -181,9 +177,9 @@ def form_duplane : GICombineRule <
181177
(apply [{ applyDupLane(*${root}, MRI, B, ${matchinfo}); }])
182178
>;
183179

184-
def shuffle_vector_lowering : GICombineGroup<[dup, rev, ext, zip, uzp, trn, fullrev,
185-
fullrevpoison, form_duplane,
186-
shuf_to_ins]>;
180+
def shuffle_vector_lowering
181+
: GICombineGroup<[dup, rev, ext, zip, uzp, trn, fullrev, form_duplane,
182+
shuf_to_ins]>;
187183

188184
// Turn G_UNMERGE_VALUES -> G_EXTRACT_VECTOR_ELT's
189185
def vector_unmerge_lowering : GICombineRule <

‎llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -710,7 +710,7 @@ define <3 x i16> @v3i16_func_void() #0 {
710710
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_POISON
711711
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s16>) = G_LOAD [[DEF]](p1) :: (load (<3 x s16>) from `ptr addrspace(1) poison`, align 8, addrspace 1)
712712
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[LOAD]](<3 x s16>)
713-
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s16) = G_POISON
713+
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
714714
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV]](s16), [[UV1]](s16), [[UV2]](s16), [[DEF1]](s16)
715715
; CHECK-NEXT: [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s16>)
716716
; CHECK-NEXT: $vgpr0 = COPY [[UV3]](<2 x s16>)
@@ -753,7 +753,7 @@ define <5 x i16> @v5i16_func_void() #0 {
753753
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (volatile invariant load (p1) from `ptr addrspace(4) poison`, addrspace 4)
754754
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<5 x s16>) = G_LOAD [[LOAD]](p1) :: (load (<5 x s16>) from %ir.ptr, align 16, addrspace 1)
755755
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[LOAD1]](<5 x s16>)
756-
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s16) = G_POISON
756+
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
757757
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<6 x s16>) = G_BUILD_VECTOR [[UV]](s16), [[UV1]](s16), [[UV2]](s16), [[UV3]](s16), [[UV4]](s16), [[DEF1]](s16)
758758
; CHECK-NEXT: [[UV5:%[0-9]+]]:_(<2 x s16>), [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<6 x s16>)
759759
; CHECK-NEXT: $vgpr0 = COPY [[UV5]](<2 x s16>)

‎llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval
3939
; GCN-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]
4040
; GCN-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]
4141
; GCN-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]
42-
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_POISON
42+
; GCN-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
4343
; GCN-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
4444
; GCN-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
4545
; GCN-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10

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