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[InstCombine] Add select of clamped shifts test coverage based off #109888
Add baseline tests for removing shift amount clamps which are also bound by a select: Fold (select (icmp_ugt A, BW-1), (shift X, (and A, C)), Y) --> (select (icmp_ugt A, BW-1), (shift X, A), T) Fold (select (icmp_ugt A, BW-1), Y, (shift X, (umin A, C))) --> (select (icmp_ugt A, BW-1), Y, (shift X, A))
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‎llvm/test/Transforms/InstCombine/select-shift-clamp.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -passes=instcombine < %s | FileCheck %s
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declare void @use_i17(i17)
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declare void @use_i32(i32)
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; Fold (select (icmp_ugt A, BW-1), (shift X, (and A, C)), FalseVal)
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; --> (select (icmp_ugt A, BW-1), (shift X, A), FalseVal)
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; Fold (select (icmp_ult A, BW), (shift X, (and A, C)), FalseVal)
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; --> (select (icmp_ult A, BW), (shift X, A), FalseVal)
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; iff Pow2 element width and C masks all amt bits.
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define i32 @select_ult_shl_clamp_and_i32(i32 %a0, i32 %a1, i32 %a2) {
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; CHECK-LABEL: @select_ult_shl_clamp_and_i32(
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; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[A1:%.*]], 32
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; CHECK-NEXT: [[M:%.*]] = and i32 [[A1]], 31
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; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[A0:%.*]], [[M]]
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; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i32 [[TMP1]], i32 [[A2:%.*]]
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; CHECK-NEXT: ret i32 [[R]]
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;
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%c = icmp ult i32 %a1, 32
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%m = and i32 %a1, 31
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%s = shl i32 %a0, %m
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%r = select i1 %c, i32 %s, i32 %a2
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ret i32 %r
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}
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define i32 @select_ule_ashr_clamp_and_i32(i32 %a0, i32 %a1, i32 %a2) {
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; CHECK-LABEL: @select_ule_ashr_clamp_and_i32(
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; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[A1:%.*]], 32
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; CHECK-NEXT: [[M:%.*]] = and i32 [[A1]], 127
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; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[A0:%.*]], [[M]]
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; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i32 [[TMP1]], i32 [[A2:%.*]]
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; CHECK-NEXT: ret i32 [[R]]
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;
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%c = icmp ule i32 %a1, 31
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%m = and i32 %a1, 127
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%s = ashr i32 %a0, %m
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%r = select i1 %c, i32 %s, i32 %a2
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ret i32 %r
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}
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define i32 @select_ugt_lshr_clamp_and_i32(i32 %a0, i32 %a1, i32 %a2) {
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; CHECK-LABEL: @select_ugt_lshr_clamp_and_i32(
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; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[A1:%.*]], 31
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; CHECK-NEXT: [[M:%.*]] = and i32 [[A1]], 31
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; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[A0:%.*]], [[M]]
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; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i32 [[A2:%.*]], i32 [[TMP1]]
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; CHECK-NEXT: ret i32 [[R]]
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;
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%c = icmp ugt i32 %a1, 31
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%m = and i32 %a1, 31
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%s = lshr i32 %a0, %m
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%r = select i1 %c, i32 %a2, i32 %s
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ret i32 %r
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}
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define i32 @select_uge_shl_clamp_and_i32(i32 %a0, i32 %a1, i32 %a2) {
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; CHECK-LABEL: @select_uge_shl_clamp_and_i32(
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; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[A1:%.*]], 31
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; CHECK-NEXT: [[M:%.*]] = and i32 [[A1]], 63
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; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[A0:%.*]], [[M]]
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; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i32 [[A2:%.*]], i32 [[TMP1]]
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; CHECK-NEXT: ret i32 [[R]]
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;
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%c = icmp uge i32 %a1, 32
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%m = and i32 %a1, 63
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%s = shl i32 %a0, %m
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%r = select i1 %c, i32 %a2, i32 %s
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ret i32 %r
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}
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; negative test - multiuse
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define i32 @select_ule_ashr_clamp_and_i32_multiuse(i32 %a0, i32 %a1, i32 %a2) {
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; CHECK-LABEL: @select_ule_ashr_clamp_and_i32_multiuse(
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; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[A1:%.*]], 32
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; CHECK-NEXT: [[M:%.*]] = and i32 [[A1]], 127
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; CHECK-NEXT: [[S:%.*]] = ashr i32 [[A0:%.*]], [[M]]
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; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i32 [[S]], i32 [[A2:%.*]]
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; CHECK-NEXT: call void @use_i32(i32 [[S]])
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; CHECK-NEXT: ret i32 [[R]]
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;
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%c = icmp ule i32 %a1, 31
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%m = and i32 %a1, 127
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%s = ashr i32 %a0, %m
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%r = select i1 %c, i32 %s, i32 %a2
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call void @use_i32(i32 %s)
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ret i32 %r
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}
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; negative test - mask doesn't cover all legal amount bit
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define i32 @select_ult_shl_clamp_and_i32_badmask(i32 %a0, i32 %a1, i32 %a2) {
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; CHECK-LABEL: @select_ult_shl_clamp_and_i32_badmask(
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; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[A1:%.*]], 32
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; CHECK-NEXT: [[M:%.*]] = and i32 [[A1]], 28
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; CHECK-NEXT: [[S:%.*]] = shl i32 [[A0:%.*]], [[M]]
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; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i32 [[S]], i32 [[A2:%.*]]
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; CHECK-NEXT: ret i32 [[R]]
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;
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%c = icmp ult i32 %a1, 32
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%m = and i32 %a1, 28
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%s = shl i32 %a0, %m
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%r = select i1 %c, i32 %s, i32 %a2
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ret i32 %r
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}
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; negative test - non-pow2
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define i17 @select_uge_lshr_clamp_and_i17_nonpow2(i17 %a0, i17 %a1, i17 %a2) {
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; CHECK-LABEL: @select_uge_lshr_clamp_and_i17_nonpow2(
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; CHECK-NEXT: [[C:%.*]] = icmp ugt i17 [[A1:%.*]], 16
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; CHECK-NEXT: [[M:%.*]] = and i17 [[A1]], 255
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; CHECK-NEXT: [[S:%.*]] = lshr i17 [[A0:%.*]], [[M]]
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; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i17 [[A2:%.*]], i17 [[S]]
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; CHECK-NEXT: ret i17 [[R]]
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;
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%c = icmp uge i17 %a1, 17
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%m = and i17 %a1, 255
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%s = lshr i17 %a0, %m
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%r = select i1 %c, i17 %a2, i17 %s
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ret i17 %r
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}
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; Fold (select (icmp_ugt A, BW-1), TrueVal, (shift X, (umin A, C)))
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; --> (select (icmp_ugt A, BW-1), TrueVal, (shift X, A))
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; Fold (select (icmp_ult A, BW), (shift X, (umin A, C)), FalseVal)
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; --> (select (icmp_ult A, BW), (shift X, A), FalseVal)
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; iff C >= BW-1
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define i32 @select_ult_shl_clamp_umin_i32(i32 %a0, i32 %a1, i32 %a2) {
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; CHECK-LABEL: @select_ult_shl_clamp_umin_i32(
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; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[A1:%.*]], 32
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; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.umin.i32(i32 [[A1]], i32 31)
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; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[A0:%.*]], [[M]]
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; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i32 [[TMP1]], i32 [[A2:%.*]]
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; CHECK-NEXT: ret i32 [[R]]
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;
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%c = icmp ult i32 %a1, 32
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%m = call i32 @llvm.umin.i32(i32 %a1, i32 31)
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%s = shl i32 %a0, %m
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%r = select i1 %c, i32 %s, i32 %a2
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ret i32 %r
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}
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define i17 @select_ule_ashr_clamp_umin_i17(i17 %a0, i17 %a1, i17 %a2) {
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; CHECK-LABEL: @select_ule_ashr_clamp_umin_i17(
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; CHECK-NEXT: [[C:%.*]] = icmp ult i17 [[A1:%.*]], 17
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; CHECK-NEXT: [[M:%.*]] = call i17 @llvm.umin.i17(i17 [[A1]], i17 17)
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; CHECK-NEXT: [[TMP1:%.*]] = ashr i17 [[A0:%.*]], [[M]]
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; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i17 [[TMP1]], i17 [[A2:%.*]]
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; CHECK-NEXT: ret i17 [[R]]
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;
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%c = icmp ule i17 %a1, 16
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%m = call i17 @llvm.umin.i17(i17 %a1, i17 17)
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%s = ashr i17 %a0, %m
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%r = select i1 %c, i17 %s, i17 %a2
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ret i17 %r
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}
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define i32 @select_ugt_shl_clamp_umin_i32(i32 %a0, i32 %a1, i32 %a2) {
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; CHECK-LABEL: @select_ugt_shl_clamp_umin_i32(
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; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[A1:%.*]], 31
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; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.umin.i32(i32 [[A1]], i32 128)
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; CHECK-NEXT: [[S:%.*]] = shl i32 [[A0:%.*]], [[M]]
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; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i32 [[A2:%.*]], i32 [[S]]
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; CHECK-NEXT: ret i32 [[R]]
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;
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%c = icmp ugt i32 %a1, 31
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%m = call i32 @llvm.umin.i32(i32 %a1, i32 128)
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%s = shl i32 %a0, %m
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%r = select i1 %c, i32 %a2, i32 %s
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ret i32 %r
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}
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define <2 x i32> @select_uge_lshr_clamp_umin_v2i32(<2 x i32> %a0, <2 x i32> %a1, <2 x i32> %a2) {
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; CHECK-LABEL: @select_uge_lshr_clamp_umin_v2i32(
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; CHECK-NEXT: [[C:%.*]] = icmp ugt <2 x i32> [[A1:%.*]], <i32 31, i32 31>
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; CHECK-NEXT: [[M:%.*]] = call <2 x i32> @llvm.umin.v2i32(<2 x i32> [[A1]], <2 x i32> <i32 63, i32 31>)
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; CHECK-NEXT: [[S:%.*]] = lshr <2 x i32> [[A0:%.*]], [[M]]
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; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[C]], <2 x i32> [[A2:%.*]], <2 x i32> [[S]]
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; CHECK-NEXT: ret <2 x i32> [[R]]
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;
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%c = icmp uge <2 x i32> %a1, <i32 32, i32 32>
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%m = call <2 x i32> @llvm.umin.v2i32(<2 x i32> %a1, <2 x i32> <i32 63, i32 31>)
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%s = lshr <2 x i32> %a0, %m
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%r = select <2 x i1> %c, <2 x i32> %a2, <2 x i32> %s
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ret <2 x i32> %r
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}
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; negative test - multiuse
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define i32 @select_ugt_shl_clamp_umin_i32_multiuse(i32 %a0, i32 %a1, i32 %a2) {
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; CHECK-LABEL: @select_ugt_shl_clamp_umin_i32_multiuse(
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; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[A1:%.*]], 32
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; CHECK-NEXT: [[M:%.*]] = call i32 @llvm.umin.i32(i32 [[A1]], i32 128)
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; CHECK-NEXT: [[S:%.*]] = shl i32 [[A0:%.*]], [[M]]
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; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i32 [[A2:%.*]], i32 [[S]]
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; CHECK-NEXT: call void @use_i32(i32 [[S]])
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; CHECK-NEXT: ret i32 [[R]]
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;
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%c = icmp ugt i32 %a1, 32
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%m = call i32 @llvm.umin.i32(i32 %a1, i32 128)
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%s = shl i32 %a0, %m
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%r = select i1 %c, i32 %a2, i32 %s
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call void @use_i32(i32 %s)
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ret i32 %r
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}
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; negative test - umin limit doesn't cover all legal amounts
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define i17 @select_uge_lshr_clamp_umin_i17_badlimit(i17 %a0, i17 %a1, i17 %a2) {
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; CHECK-LABEL: @select_uge_lshr_clamp_umin_i17_badlimit(
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; CHECK-NEXT: [[C:%.*]] = icmp ugt i17 [[A1:%.*]], 15
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; CHECK-NEXT: [[M:%.*]] = call i17 @llvm.umin.i17(i17 [[A1]], i17 12)
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; CHECK-NEXT: [[S:%.*]] = lshr i17 [[A0:%.*]], [[M]]
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; CHECK-NEXT: [[R:%.*]] = select i1 [[C]], i17 [[A2:%.*]], i17 [[S]]
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; CHECK-NEXT: ret i17 [[R]]
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;
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%c = icmp uge i17 %a1, 16
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%m = call i17 @llvm.umin.i17(i17 %a1, i17 12)
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%s = lshr i17 %a0, %m
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%r = select i1 %c, i17 %a2, i17 %s
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ret i17 %r
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}
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define range(i64 0, -9223372036854775807) <4 x i64> @PR109888(<4 x i64> %0) {
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; CHECK-LABEL: @PR109888(
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; CHECK-NEXT: [[C:%.*]] = icmp ult <4 x i64> [[TMP0:%.*]], <i64 64, i64 64, i64 64, i64 64>
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; CHECK-NEXT: [[M:%.*]] = and <4 x i64> [[TMP0]], <i64 63, i64 63, i64 63, i64 63>
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; CHECK-NEXT: [[TMP2:%.*]] = shl nuw <4 x i64> <i64 1, i64 1, i64 1, i64 1>, [[M]]
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; CHECK-NEXT: [[R:%.*]] = select <4 x i1> [[C]], <4 x i64> [[TMP2]], <4 x i64> zeroinitializer
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; CHECK-NEXT: ret <4 x i64> [[R]]
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;
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%c = icmp ult <4 x i64> %0, <i64 64, i64 64, i64 64, i64 64>
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%m = and <4 x i64> %0, <i64 63, i64 63, i64 63, i64 63>
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%s = shl nuw <4 x i64> <i64 1, i64 1, i64 1, i64 1>, %m
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%r = select <4 x i1> %c, <4 x i64> %s, <4 x i64> zeroinitializer
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ret <4 x i64> %r
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}

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