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Revert "[SelectionDAG] Add STRICT_BF16_TO_FP and STRICT_FP_TO_BF16 (#80056)"
This reverts commit b0c158b. The changes in `compiler-rt` broke tests.
1 parent e6e53ca commit 2c5d01c

14 files changed

+23
-283
lines changed

‎compiler-rt/lib/builtins/CMakeLists.txt

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -190,7 +190,6 @@ set(GENERIC_SOURCES
190190

191191
# We only build BF16 files when "__bf16" is available.
192192
set(BF16_SOURCES
193-
extendbfsf2.c
194193
truncdfbf2.c
195194
truncsfbf2.c
196195
)

‎compiler-rt/lib/builtins/extendbfsf2.c

Lines changed: 0 additions & 13 deletions
This file was deleted.

‎compiler-rt/lib/builtins/fp_extend.h

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -81,13 +81,6 @@ static inline int src_rep_t_clz_impl(src_rep_t a) {
8181

8282
#define src_rep_t_clz src_rep_t_clz_impl
8383

84-
#elif defined SRC_BFLOAT
85-
typedef __bf16 src_t;
86-
typedef uint16_t src_rep_t;
87-
#define SRC_REP_C UINT16_C
88-
static const int srcSigBits = 7;
89-
#define src_rep_t_clz __builtin_clz
90-
9184
#else
9285
#error Source should be half, single, or double precision!
9386
#endif // end source precision

‎llvm/include/llvm/CodeGen/ISDOpcodes.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -921,8 +921,6 @@ enum NodeType {
921921
/// has native conversions.
922922
BF16_TO_FP,
923923
FP_TO_BF16,
924-
STRICT_BF16_TO_FP,
925-
STRICT_FP_TO_BF16,
926924

927925
/// Perform various unary floating-point operations inspired by libm. For
928926
/// FPOWI, the result is undefined if the integer operand doesn't fit into

‎llvm/include/llvm/CodeGen/SelectionDAGNodes.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -698,8 +698,6 @@ END_TWO_BYTE_PACK()
698698
return false;
699699
case ISD::STRICT_FP16_TO_FP:
700700
case ISD::STRICT_FP_TO_FP16:
701-
case ISD::STRICT_BF16_TO_FP:
702-
case ISD::STRICT_FP_TO_BF16:
703701
#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
704702
case ISD::STRICT_##DAGN:
705703
#include "llvm/IR/ConstrainedOps.def"

‎llvm/include/llvm/IR/RuntimeLibcalls.def

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -304,7 +304,6 @@ HANDLE_LIBCALL(FEGETMODE, "fegetmode")
304304
HANDLE_LIBCALL(FESETMODE, "fesetmode")
305305

306306
// Conversion
307-
HANDLE_LIBCALL(FPEXT_BF16_F32, "__extendbfsf2")
308307
HANDLE_LIBCALL(FPEXT_F32_PPCF128, "__gcc_stoq")
309308
HANDLE_LIBCALL(FPEXT_F64_PPCF128, "__gcc_dtoq")
310309
HANDLE_LIBCALL(FPEXT_F80_F128, "__extendxftf2")

‎llvm/include/llvm/Target/TargetSelectionDAG.td

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -541,8 +541,6 @@ def fp_to_sint_sat : SDNode<"ISD::FP_TO_SINT_SAT" , SDTFPToIntSatOp>;
541541
def fp_to_uint_sat : SDNode<"ISD::FP_TO_UINT_SAT" , SDTFPToIntSatOp>;
542542
def f16_to_fp : SDNode<"ISD::FP16_TO_FP" , SDTIntToFPOp>;
543543
def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>;
544-
def bf16_to_fp : SDNode<"ISD::BF16_TO_FP" , SDTIntToFPOp>;
545-
def fp_to_bf16 : SDNode<"ISD::FP_TO_BF16" , SDTFPToIntOp>;
546544

547545
def strict_fadd : SDNode<"ISD::STRICT_FADD",
548546
SDTFPBinOp, [SDNPHasChain, SDNPCommutative]>;
@@ -622,11 +620,6 @@ def strict_f16_to_fp : SDNode<"ISD::STRICT_FP16_TO_FP",
622620
def strict_fp_to_f16 : SDNode<"ISD::STRICT_FP_TO_FP16",
623621
SDTFPToIntOp, [SDNPHasChain]>;
624622

625-
def strict_bf16_to_fp : SDNode<"ISD::STRICT_BF16_TO_FP",
626-
SDTIntToFPOp, [SDNPHasChain]>;
627-
def strict_fp_to_bf16 : SDNode<"ISD::STRICT_FP_TO_BF16",
628-
SDTFPToIntOp, [SDNPHasChain]>;
629-
630623
def strict_fsetcc : SDNode<"ISD::STRICT_FSETCC", SDTSetCC, [SDNPHasChain]>;
631624
def strict_fsetccs : SDNode<"ISD::STRICT_FSETCCS", SDTSetCC, [SDNPHasChain]>;
632625

@@ -1598,12 +1591,6 @@ def any_f16_to_fp : PatFrags<(ops node:$src),
15981591
def any_fp_to_f16 : PatFrags<(ops node:$src),
15991592
[(fp_to_f16 node:$src),
16001593
(strict_fp_to_f16 node:$src)]>;
1601-
def any_bf16_to_fp : PatFrags<(ops node:$src),
1602-
[(bf16_to_fp node:$src),
1603-
(strict_bf16_to_fp node:$src)]>;
1604-
def any_fp_to_bf16 : PatFrags<(ops node:$src),
1605-
[(fp_to_bf16 node:$src),
1606-
(strict_fp_to_bf16 node:$src)]>;
16071594

16081595
multiclass binary_atomic_op_ord {
16091596
def NAME#_monotonic : PatFrag<(ops node:$ptr, node:$val),

‎llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Lines changed: 9 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -1047,7 +1047,6 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
10471047
Node->getOperand(0).getValueType());
10481048
break;
10491049
case ISD::STRICT_FP_TO_FP16:
1050-
case ISD::STRICT_FP_TO_BF16:
10511050
case ISD::STRICT_SINT_TO_FP:
10521051
case ISD::STRICT_UINT_TO_FP:
10531052
case ISD::STRICT_LRINT:
@@ -3646,14 +3645,14 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
36463645
DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res));
36473646
}
36483647
break;
3649-
case ISD::STRICT_BF16_TO_FP:
36503648
case ISD::STRICT_FP16_TO_FP:
36513649
if (Node->getValueType(0) != MVT::f32) {
36523650
// We can extend to types bigger than f32 in two steps without changing
36533651
// the result. Since "f16 -> f32" is much more commonly available, give
36543652
// CodeGen the option of emitting that before resorting to a libcall.
3655-
SDValue Res = DAG.getNode(Node->getOpcode(), dl, {MVT::f32, MVT::Other},
3656-
{Node->getOperand(0), Node->getOperand(1)});
3653+
SDValue Res =
3654+
DAG.getNode(ISD::STRICT_FP16_TO_FP, dl, {MVT::f32, MVT::Other},
3655+
{Node->getOperand(0), Node->getOperand(1)});
36573656
Res = DAG.getNode(ISD::STRICT_FP_EXTEND, dl,
36583657
{Node->getValueType(0), MVT::Other},
36593658
{Res.getValue(1), Res});
@@ -4652,16 +4651,6 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
46524651
Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false).first);
46534652
}
46544653
break;
4655-
case ISD::STRICT_BF16_TO_FP:
4656-
if (Node->getValueType(0) == MVT::f32) {
4657-
TargetLowering::MakeLibCallOptions CallOptions;
4658-
std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(
4659-
DAG, RTLIB::FPEXT_BF16_F32, MVT::f32, Node->getOperand(1),
4660-
CallOptions, SDLoc(Node), Node->getOperand(0));
4661-
Results.push_back(Tmp.first);
4662-
Results.push_back(Tmp.second);
4663-
}
4664-
break;
46654654
case ISD::STRICT_FP16_TO_FP: {
46664655
if (Node->getValueType(0) == MVT::f32) {
46674656
TargetLowering::MakeLibCallOptions CallOptions;
@@ -4803,17 +4792,12 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
48034792
break;
48044793
}
48054794
case ISD::STRICT_FP_EXTEND:
4806-
case ISD::STRICT_FP_TO_FP16:
4807-
case ISD::STRICT_FP_TO_BF16: {
4808-
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4809-
if (Node->getOpcode() == ISD::STRICT_FP_TO_FP16)
4810-
LC = RTLIB::getFPROUND(Node->getOperand(1).getValueType(), MVT::f16);
4811-
else if (Node->getOpcode() == ISD::STRICT_FP_TO_BF16)
4812-
LC = RTLIB::getFPROUND(Node->getOperand(1).getValueType(), MVT::bf16);
4813-
else
4814-
LC = RTLIB::getFPEXT(Node->getOperand(1).getValueType(),
4815-
Node->getValueType(0));
4816-
4795+
case ISD::STRICT_FP_TO_FP16: {
4796+
RTLIB::Libcall LC =
4797+
Node->getOpcode() == ISD::STRICT_FP_TO_FP16
4798+
? RTLIB::getFPROUND(Node->getOperand(1).getValueType(), MVT::f16)
4799+
: RTLIB::getFPEXT(Node->getOperand(1).getValueType(),
4800+
Node->getValueType(0));
48174801
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to legalize as libcall");
48184802

48194803
TargetLowering::MakeLibCallOptions CallOptions;

‎llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

Lines changed: 14 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -918,7 +918,6 @@ bool DAGTypeLegalizer::SoftenFloatOperand(SDNode *N, unsigned OpNo) {
918918
case ISD::STRICT_FP_TO_FP16:
919919
case ISD::FP_TO_FP16: // Same as FP_ROUND for softening purposes
920920
case ISD::FP_TO_BF16:
921-
case ISD::STRICT_FP_TO_BF16:
922921
case ISD::STRICT_FP_ROUND:
923922
case ISD::FP_ROUND: Res = SoftenFloatOp_FP_ROUND(N); break;
924923
case ISD::STRICT_FP_TO_SINT:
@@ -971,7 +970,6 @@ SDValue DAGTypeLegalizer::SoftenFloatOp_FP_ROUND(SDNode *N) {
971970
assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16 ||
972971
N->getOpcode() == ISD::STRICT_FP_TO_FP16 ||
973972
N->getOpcode() == ISD::FP_TO_BF16 ||
974-
N->getOpcode() == ISD::STRICT_FP_TO_BF16 ||
975973
N->getOpcode() == ISD::STRICT_FP_ROUND);
976974

977975
bool IsStrict = N->isStrictFPOpcode();
@@ -982,8 +980,7 @@ SDValue DAGTypeLegalizer::SoftenFloatOp_FP_ROUND(SDNode *N) {
982980
if (N->getOpcode() == ISD::FP_TO_FP16 ||
983981
N->getOpcode() == ISD::STRICT_FP_TO_FP16)
984982
FloatRVT = MVT::f16;
985-
else if (N->getOpcode() == ISD::FP_TO_BF16 ||
986-
N->getOpcode() == ISD::STRICT_FP_TO_BF16)
983+
else if (N->getOpcode() == ISD::FP_TO_BF16)
987984
FloatRVT = MVT::bf16;
988985

989986
RTLIB::Libcall LC = RTLIB::getFPROUND(SVT, FloatRVT);
@@ -2196,11 +2193,13 @@ static ISD::NodeType GetPromotionOpcodeStrict(EVT OpVT, EVT RetVT) {
21962193
if (RetVT == MVT::f16)
21972194
return ISD::STRICT_FP_TO_FP16;
21982195

2199-
if (OpVT == MVT::bf16)
2200-
return ISD::STRICT_BF16_TO_FP;
2196+
if (OpVT == MVT::bf16) {
2197+
// TODO: return ISD::STRICT_BF16_TO_FP;
2198+
}
22012199

2202-
if (RetVT == MVT::bf16)
2203-
return ISD::STRICT_FP_TO_BF16;
2200+
if (RetVT == MVT::bf16) {
2201+
// TODO: return ISD::STRICT_FP_TO_BF16;
2202+
}
22042203

22052204
report_fatal_error("Attempt at an invalid promotion-related conversion");
22062205
}
@@ -3000,16 +2999,10 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfRes_FP_ROUND(SDNode *N) {
30002999
EVT SVT = N->getOperand(0).getValueType();
30013000

30023001
if (N->isStrictFPOpcode()) {
3003-
// FIXME: assume we only have two f16 variants for now.
3004-
unsigned Opcode;
3005-
if (RVT == MVT::f16)
3006-
Opcode = ISD::STRICT_FP_TO_FP16;
3007-
else if (RVT == MVT::bf16)
3008-
Opcode = ISD::STRICT_FP_TO_BF16;
3009-
else
3010-
llvm_unreachable("unknown half type");
3011-
SDValue Res = DAG.getNode(Opcode, SDLoc(N), {MVT::i16, MVT::Other},
3012-
{N->getOperand(0), N->getOperand(1)});
3002+
assert(RVT == MVT::f16);
3003+
SDValue Res =
3004+
DAG.getNode(ISD::STRICT_FP_TO_FP16, SDLoc(N), {MVT::i16, MVT::Other},
3005+
{N->getOperand(0), N->getOperand(1)});
30133006
ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
30143007
return Res;
30153008
}
@@ -3199,16 +3192,10 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfOp_FP_EXTEND(SDNode *N) {
31993192
Op = GetSoftPromotedHalf(N->getOperand(IsStrict ? 1 : 0));
32003193

32013194
if (IsStrict) {
3202-
unsigned Opcode;
3203-
if (SVT == MVT::f16)
3204-
Opcode = ISD::STRICT_FP16_TO_FP;
3205-
else if (SVT == MVT::bf16)
3206-
Opcode = ISD::STRICT_BF16_TO_FP;
3207-
else
3208-
llvm_unreachable("unknown half type");
3195+
assert(SVT == MVT::f16);
32093196
SDValue Res =
3210-
DAG.getNode(Opcode, SDLoc(N), {N->getValueType(0), MVT::Other},
3211-
{N->getOperand(0), Op});
3197+
DAG.getNode(ISD::STRICT_FP16_TO_FP, SDLoc(N),
3198+
{N->getValueType(0), MVT::Other}, {N->getOperand(0), Op});
32123199
ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
32133200
ReplaceValueWith(SDValue(N, 0), Res);
32143201
return SDValue();

‎llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -165,7 +165,6 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
165165
case ISD::FP_TO_FP16:
166166
Res = PromoteIntRes_FP_TO_FP16_BF16(N);
167167
break;
168-
case ISD::STRICT_FP_TO_BF16:
169168
case ISD::STRICT_FP_TO_FP16:
170169
Res = PromoteIntRes_STRICT_FP_TO_FP16_BF16(N);
171170
break;

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -380,9 +380,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
380380
case ISD::FP_TO_FP16: return "fp_to_fp16";
381381
case ISD::STRICT_FP_TO_FP16: return "strict_fp_to_fp16";
382382
case ISD::BF16_TO_FP: return "bf16_to_fp";
383-
case ISD::STRICT_BF16_TO_FP: return "strict_bf16_to_fp";
384383
case ISD::FP_TO_BF16: return "fp_to_bf16";
385-
case ISD::STRICT_FP_TO_BF16: return "strict_fp_to_bf16";
386384
case ISD::LROUND: return "lround";
387385
case ISD::STRICT_LROUND: return "strict_lround";
388386
case ISD::LLROUND: return "llround";

‎llvm/lib/CodeGen/TargetLoweringBase.cpp

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -307,9 +307,6 @@ RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
307307
} else if (OpVT == MVT::f80) {
308308
if (RetVT == MVT::f128)
309309
return FPEXT_F80_F128;
310-
} else if (OpVT == MVT::bf16) {
311-
if (RetVT == MVT::f32)
312-
return FPEXT_BF16_F32;
313310
}
314311

315312
return UNKNOWN_LIBCALL;

‎llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -406,11 +406,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
406406
setOperationAction(Op, MVT::f128, Expand);
407407
}
408408

409-
for (auto VT : {MVT::f32, MVT::f64, MVT::f80, MVT::f128}) {
410-
setOperationAction(ISD::STRICT_FP_TO_BF16, VT, Expand);
411-
setOperationAction(ISD::STRICT_BF16_TO_FP, VT, Expand);
412-
}
413-
414409
for (MVT VT : {MVT::f32, MVT::f64, MVT::f80, MVT::f128}) {
415410
setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
416411
setLoadExtAction(ISD::EXTLOAD, VT, MVT::bf16, Expand);

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