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RoboTuxRoboTux
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[MLIR][Linalg] Fix insert_slice fusion with rank reduction (#130961)
Insert_slice fusion with a linalg producer does not account for possible rank-reduction in the insert_slice return type. When that happens, a tensor.cast gets generated due to the type mismatch which is invalid for tensor with different rank. This later trips other pass.
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4 files changed

+126
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‎mlir/include/mlir/Dialect/Tensor/Utils/Utils.h

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@@ -43,6 +43,11 @@ FailureOr<RankedTensorType>
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computeTransposedType(RankedTensorType rankedTensorType,
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ArrayRef<int64_t> transposeVector);
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/// Create tensor.collapse_shape to drop unit dimensions in `dropDims` in tensor
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/// `src`.
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CollapseShapeOp dropGivenUnitDims(OpBuilder &b, Location loc, Value src,
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const llvm::SmallBitVector &dropDims);
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/// A tensor.insert_slice is a cast-like operation if it merely rank-extends the
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/// source tensor or inserts the source tensor into a destination tensor with
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/// the same shape.

‎mlir/lib/Dialect/Linalg/Transforms/Fusion.cpp

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@@ -18,6 +18,7 @@
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#include "mlir/Dialect/Linalg/Utils/Utils.h"
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#include "mlir/Dialect/MemRef/IR/MemRef.h"
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#include "mlir/Dialect/Tensor/IR/Tensor.h"
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#include "mlir/Dialect/Tensor/Utils/Utils.h"
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#include "mlir/IR/AffineExpr.h"
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#include "mlir/IR/AffineMap.h"
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#include "mlir/IR/Dominance.h"
@@ -26,6 +27,7 @@
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#include "mlir/Transforms/RegionUtils.h"
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#include "llvm/ADT/MapVector.h"
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#include "llvm/ADT/ScopeExit.h"
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#include "llvm/ADT/SmallBitVector.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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@@ -271,12 +273,20 @@ mlir::linalg::fuseProducerOfTensor(OpBuilder &b, OpResult producerOpResult,
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consumerOpOperand);
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// Replace use.
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Value def = fusedProducer->getResult(producerOpResult.getResultNumber());
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Type consumerType = consumerOpOperand.get().getType();
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// Check if rank-reduction occurred as part of the extract_slice. If yes,
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// collapse the dropped dimensions.
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if (cast<ShapedType>(consumerType).getRank() !=
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cast<ShapedType>(def.getType()).getRank()) {
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llvm::SmallBitVector droppedDims = sliceOp.getDroppedDims();
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def =
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tensor::dropGivenUnitDims(b, fusedProducer.getLoc(), def, droppedDims);
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}
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// Canonicalizations are not guaranteed to have happened before constructing
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// `fusedProducer`. In the tensor case this can result in temporary type
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// mismatches. Insert a `tensor.cast` op to propagate the transformation
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// invariant that types are compatible.
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Value def = fusedProducer->getResult(producerOpResult.getResultNumber());
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Type consumerType = consumerOpOperand.get().getType();
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if (consumerType != def.getType())
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def = b.create<tensor::CastOp>(fusedProducer.getLoc(), consumerType, def);
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consumerOpOperand.set(def);

‎mlir/lib/Dialect/Tensor/Utils/Utils.cpp

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@@ -94,6 +94,37 @@ mlir::tensor::computeTransposedType(RankedTensorType rankedTensorType,
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return transposedTensorType;
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}
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CollapseShapeOp
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mlir::tensor::dropGivenUnitDims(OpBuilder &b, Location loc, Value src,
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const llvm::SmallBitVector &dropDims) {
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auto srcType = cast<ShapedType>(src.getType());
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int64_t rank = srcType.getRank();
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assert(rank == static_cast<int64_t>(dropDims.size()) &&
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"dropDims dimension does not match src tensor rank");
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assert(llvm::all_of(
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dropDims.set_bits(),
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[&](unsigned dim) { return srcType.getShape()[dim] == 1; }) &&
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"Dropping non unit dimension");
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// Computed reassociation map for the corresponding tensor.collapse_shape.
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SmallVector<ReassociationIndices, 2> reassocMaps;
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// Current reassociation group to add dropped dimension to.
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int64_t nextDimToGroup = 0;
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llvm::SmallBitVector keptDims(dropDims);
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keptDims.flip();
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int64_t lastSetBit = keptDims.find_last();
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for (int64_t setBit : keptDims.set_bits()) {
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// Group consecutive dropped dimension with the next non-dropped dimension.
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// If this is the last set dimension, also group all subsequent dropped
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// dimension, if any.
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int64_t upTo = setBit == lastSetBit ? rank - 1 : setBit;
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auto seq = llvm::seq_inclusive(nextDimToGroup, upTo);
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reassocMaps.emplace_back(llvm::make_range(seq.begin(), seq.end()));
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nextDimToGroup = setBit + 1;
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}
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return b.create<tensor::CollapseShapeOp>(loc, src, reassocMaps);
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}
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bool mlir::tensor::isCastLikeInsertSliceOp(InsertSliceOp op) {
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llvm::SmallBitVector droppedDims = op.getDroppedDims();
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int64_t srcDim = 0;

‎mlir/test/Dialect/Linalg/tile-and-fuse-tensors.mlir

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@@ -318,3 +318,81 @@ func.func @pad_generic_static(%small_input: tensor<58x1xf32>, %large_input: tens
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}
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return %for0 : tensor<64x128xf32>
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}
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// -----
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#map0 = affine_map<(d0, d1, d2, d3) -> (d0, d1, d3)>
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#map1 = affine_map<(d0, d1, d2, d3) -> (d0, d3, d2)>
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#map2 = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2)>
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#map3 = affine_map<(d0, d1, d2) -> (d0, d2)>
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#map4 = affine_map<(d0, d1, d2) -> (d2, d1)>
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#map5 = affine_map<(d0, d1, d2) -> (d0, d1)>
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func.func @rank_reduced_extract_slice(
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%prod_in: tensor<1x6x5xf32>, %prod_weight: tensor<1x5x6xf32>,
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%cons_in: tensor<4x6xf32>, %prod_init: tensor<1x6x6xf32>,
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%for_iv_init: tensor<4x6xf32>, %cons_init: tensor<4x2xf32>
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) -> tensor<4x6xf32> {
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%c0 = arith.constant 0 : index
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%c2 = arith.constant 2 : index
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%c6 = arith.constant 6 : index
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%mmul_prod = linalg.generic
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{indexing_maps = [#map0, #map1, #map2], iterator_types = ["parallel", "parallel", "parallel", "reduction"]}
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ins(%prod_in, %prod_weight : tensor<1x6x5xf32>, tensor<1x5x6xf32>) outs(%prod_init : tensor<1x6x6xf32>) {
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^bb0(%in: f32, %in_1: f32, %out: f32):
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%10 = arith.mulf %in, %in_1 : f32
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%11 = arith.addf %out, %10 : f32
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linalg.yield %11 : f32
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} -> tensor<1x6x6xf32>
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%for = scf.for %arg7 = %c0 to %c6 step %c2 iter_args(%arg6 = %for_iv_init) -> (tensor<4x6xf32>) {
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// Extract slice with rank-reduced result type. When fused in the loop
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// with sliced operands, the producer linalg must have its now sliced
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// result be rank-reduced as well to match consumer's use type.
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%prod_slice = tensor.extract_slice %mmul_prod[0, 0, %arg7] [1, 6, 2] [1, 1, 1] : tensor<1x6x6xf32> to tensor<6x2xf32>
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%mmul_cons = linalg.generic
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{indexing_maps = [#map3, #map4, #map5], iterator_types = ["parallel", "parallel", "reduction"]}
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ins(%cons_in, %prod_slice : tensor<4x6xf32>, tensor<6x2xf32>) outs(%cons_init : tensor<4x2xf32>) {
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^bb0(%in: f32, %in_1: f32, %out: f32):
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%20 = arith.mulf %in, %in_1 : f32
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%21 = arith.addf %out, %20 : f32
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linalg.yield %21 : f32
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} -> tensor<4x2xf32>
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%4 = tensor.insert_slice %mmul_cons into %arg6[0, %arg7] [4, 2] [1, 1] : tensor<4x2xf32> into tensor<4x6xf32>
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scf.yield %4 : tensor<4x6xf32>
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}
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return %for : tensor<4x6xf32>
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}
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// CHECK: func @rank_reduced_extract_slice(
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// CHECK-SAME: %[[PROD_IN:[0-9a-z]*]]: tensor<1x6x5xf32>
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// CHECK-SAME: %[[PROD_WEIGHT:[0-9a-z]*]]: tensor<1x5x6xf32>
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// CHECK-SAME: %[[CONS_IN:[0-9a-z]*]]: tensor<4x6xf32>
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// CHECK-SAME: %[[PROD_INIT:[0-9a-z]*]]: tensor<1x6x6xf32>
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// CHECK-SAME: %[[FOR_IV_INIT:[0-9a-z]*]]: tensor<4x6xf32>
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// CHECK-SAME: %[[CONS_INIT:[0-9a-z]*]]: tensor<4x2xf32>
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// CHECK-DAG: %[[C0:.*]] = arith.constant 0 : index
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// CHECK-DAG: %[[C2:.*]] = arith.constant 2 : index
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// CHECK-DAG: %[[C6:.*]] = arith.constant 6 : index
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// For loop right after tensor alloc & fill, no linalg.generic.
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// CHECK-NOT: linalg.generic
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// CHECK-NEXT: %[[FOR:.*]] = scf.for %[[I:[0-9a-z]*]] = %[[C0]] to %[[C6]] step %[[C2]] iter_args(%[[ARG_ITER:.*]] = %[[FOR_IV_INIT]])
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// Producer linalg.generic now inside the loop, with tiled args sliced before
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// it.
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// CHECK-DAG: %[[PROD_WEIGHT_SLICE:.*]] = tensor.extract_slice %[[PROD_WEIGHT]][0, 0, %[[I]]] [1, 5, 2] [1, 1, 1] : tensor<1x5x6xf32> to tensor<1x5x2xf32>
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// CHECK-DAG: %[[PROD_INIT_SLICE:.*]] = tensor.extract_slice %[[PROD_INIT]][0, 0, %[[I]]] [1, 6, 2] [1, 1, 1] : tensor<1x6x6xf32> to tensor<1x6x2xf32>
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// CHECK: %[[MMUL_PROD:.*]] = linalg.generic
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// CHECK-SAME: ins(%[[PROD_IN]], %[[PROD_WEIGHT_SLICE]] : tensor<1x6x5xf32>, tensor<1x5x2xf32>)
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// CHECK-SAME: outs(%[[PROD_INIT_SLICE]] : tensor<1x6x2xf32>)
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//
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// Consumer uses a rank-reduced version of producer result so a collapse_shape
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// is generated.
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// CHECK: %[[PROD_COLLAPSE:.*]] = tensor.collapse_shape %[[MMUL_PROD]] {{\[\[0, 1\], \[2\]\]}} : tensor<1x6x2xf32> into tensor<6x2xf32>
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// CHECK: %[[MMUL_CONS:.*]] = linalg.generic
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// CHECK-SAME: ins(%[[CONS_IN]], %[[PROD_COLLAPSE]] : tensor<4x6xf32>, tensor<6x2xf32>)
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// CHECK-SAME: outs(%[[CONS_INIT]] : tensor<4x2xf32>)
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// CHECK: %[[CONS_SLICE:.*]] = tensor.insert_slice %[[MMUL_CONS]] into %[[ARG_ITER]][0, %[[I]]] [4, 2] [1, 1] : tensor<4x2xf32> into tensor<4x6xf32>
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// CHECK: scf.yield %[[CONS_SLICE]] : tensor<4x6xf32>
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// CHECK: return %[[FOR]] : tensor<4x6xf32>

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