@@ -6698,6 +6698,7 @@ defm PseudoVFWREDOSUM : VPseudoVFWREDO_VS_RM;
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// 15. Vector Mask Instructions
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//===----------------------------------------------------------------------===//
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+ let Predicates = [HasVInstructions] in {
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//===----------------------------------------------------------------------===//
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// 15.1 Vector Mask-Register Logical Instructions
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//===----------------------------------------------------------------------===//
@@ -6718,7 +6719,6 @@ defm PseudoVMSET : VPseudoNullaryPseudoM<"VMXNOR">;
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//===----------------------------------------------------------------------===//
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// 15.2. Vector mask population count vcpop
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//===----------------------------------------------------------------------===//
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-
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let IsSignExtendingOpW = 1 in
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defm PseudoVCPOP: VPseudoVPOP_M;
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@@ -6753,6 +6753,7 @@ defm PseudoVIOTA_M: VPseudoVIOTA_M;
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// 15.9. Vector Element Index Instruction
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//===----------------------------------------------------------------------===//
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defm PseudoVID : VPseudoVID_V;
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+ } // Predicates = [HasVInstructions]
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//===----------------------------------------------------------------------===//
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// 16. Vector Permutation Instructions
@@ -6828,6 +6829,7 @@ let Predicates = [HasVInstructionsAnyF] in {
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//===----------------------------------------------------------------------===//
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// 16.4. Vector Register Gather Instructions
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//===----------------------------------------------------------------------===//
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+ let Predicates = [HasVInstructions] in {
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defm PseudoVRGATHER : VPseudoVGTR_VV_VX_VI<uimm5, "@earlyclobber $rd">;
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defm PseudoVRGATHEREI16 : VPseudoVGTR_VV_EEW<eew=16,
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Constraint="@earlyclobber $rd">;
@@ -6836,6 +6838,7 @@ defm PseudoVRGATHEREI16 : VPseudoVGTR_VV_EEW<eew=16,
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// 16.5. Vector Compress Instruction
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//===----------------------------------------------------------------------===//
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defm PseudoVCOMPRESS : VPseudoVCPR_V;
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+ } // Predicates = [HasVInstructions]
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//===----------------------------------------------------------------------===//
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// Patterns.
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