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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 |
| 2 | +; RUN: llc < %s -mtriple=sparcv9 | FileCheck %s -check-prefix=V9 |
| 3 | +; RUN: llc < %s -mtriple=sparcv9 -mattr=vis3 | FileCheck %s -check-prefix=VIS3 |
| 4 | + |
| 5 | +define i32 @stow(float %float) nounwind { |
| 6 | +; V9-LABEL: stow: |
| 7 | +; V9: ! %bb.0: |
| 8 | +; V9-NEXT: add %sp, -144, %sp |
| 9 | +; V9-NEXT: st %f1, [%sp+2187] |
| 10 | +; V9-NEXT: ld [%sp+2187], %o0 |
| 11 | +; V9-NEXT: retl |
| 12 | +; V9-NEXT: add %sp, 144, %sp |
| 13 | +; |
| 14 | +; VIS3-LABEL: stow: |
| 15 | +; VIS3: ! %bb.0: |
| 16 | +; VIS3-NEXT: retl |
| 17 | +; VIS3-NEXT: movstouw %f1, %o0 |
| 18 | + %w = bitcast float %float to i32 |
| 19 | + ret i32 %w |
| 20 | +} |
| 21 | + |
| 22 | +define zeroext i32 @stouw(float %float) nounwind { |
| 23 | +; V9-LABEL: stouw: |
| 24 | +; V9: ! %bb.0: |
| 25 | +; V9-NEXT: add %sp, -144, %sp |
| 26 | +; V9-NEXT: st %f1, [%sp+2187] |
| 27 | +; V9-NEXT: ld [%sp+2187], %o0 |
| 28 | +; V9-NEXT: retl |
| 29 | +; V9-NEXT: add %sp, 144, %sp |
| 30 | +; |
| 31 | +; VIS3-LABEL: stouw: |
| 32 | +; VIS3: ! %bb.0: |
| 33 | +; VIS3-NEXT: retl |
| 34 | +; VIS3-NEXT: movstouw %f1, %o0 |
| 35 | + %uw = bitcast float %float to i32 |
| 36 | + ret i32 %uw |
| 37 | +} |
| 38 | + |
| 39 | +define signext i32 @stosw(float %float) nounwind { |
| 40 | +; V9-LABEL: stosw: |
| 41 | +; V9: ! %bb.0: |
| 42 | +; V9-NEXT: add %sp, -144, %sp |
| 43 | +; V9-NEXT: st %f1, [%sp+2187] |
| 44 | +; V9-NEXT: ldsw [%sp+2187], %o0 |
| 45 | +; V9-NEXT: retl |
| 46 | +; V9-NEXT: add %sp, 144, %sp |
| 47 | +; |
| 48 | +; VIS3-LABEL: stosw: |
| 49 | +; VIS3: ! %bb.0: |
| 50 | +; VIS3-NEXT: retl |
| 51 | +; VIS3-NEXT: movstosw %f1, %o0 |
| 52 | + %sw = bitcast float %float to i32 |
| 53 | + ret i32 %sw |
| 54 | +} |
| 55 | + |
| 56 | +define float @wtos(i32 %w) nounwind { |
| 57 | +; V9-LABEL: wtos: |
| 58 | +; V9: ! %bb.0: |
| 59 | +; V9-NEXT: add %sp, -144, %sp |
| 60 | +; V9-NEXT: st %o0, [%sp+2187] |
| 61 | +; V9-NEXT: ld [%sp+2187], %f0 |
| 62 | +; V9-NEXT: retl |
| 63 | +; V9-NEXT: add %sp, 144, %sp |
| 64 | +; |
| 65 | +; VIS3-LABEL: wtos: |
| 66 | +; VIS3: ! %bb.0: |
| 67 | +; VIS3-NEXT: retl |
| 68 | +; VIS3-NEXT: movwtos %o0, %f0 |
| 69 | + %float = bitcast i32 %w to float |
| 70 | + ret float %float |
| 71 | +} |
| 72 | + |
| 73 | +define float @uwtos(i32 zeroext %uw) nounwind { |
| 74 | +; V9-LABEL: uwtos: |
| 75 | +; V9: ! %bb.0: |
| 76 | +; V9-NEXT: add %sp, -144, %sp |
| 77 | +; V9-NEXT: st %o0, [%sp+2187] |
| 78 | +; V9-NEXT: ld [%sp+2187], %f0 |
| 79 | +; V9-NEXT: retl |
| 80 | +; V9-NEXT: add %sp, 144, %sp |
| 81 | +; |
| 82 | +; VIS3-LABEL: uwtos: |
| 83 | +; VIS3: ! %bb.0: |
| 84 | +; VIS3-NEXT: retl |
| 85 | +; VIS3-NEXT: movwtos %o0, %f0 |
| 86 | + %float = bitcast i32 %uw to float |
| 87 | + ret float %float |
| 88 | +} |
| 89 | + |
| 90 | +define float @swtos(i32 signext %sw) nounwind { |
| 91 | +; V9-LABEL: swtos: |
| 92 | +; V9: ! %bb.0: |
| 93 | +; V9-NEXT: add %sp, -144, %sp |
| 94 | +; V9-NEXT: st %o0, [%sp+2187] |
| 95 | +; V9-NEXT: ld [%sp+2187], %f0 |
| 96 | +; V9-NEXT: retl |
| 97 | +; V9-NEXT: add %sp, 144, %sp |
| 98 | +; |
| 99 | +; VIS3-LABEL: swtos: |
| 100 | +; VIS3: ! %bb.0: |
| 101 | +; VIS3-NEXT: retl |
| 102 | +; VIS3-NEXT: movwtos %o0, %f0 |
| 103 | + %float = bitcast i32 %sw to float |
| 104 | + ret float %float |
| 105 | +} |
| 106 | + |
| 107 | +define i64 @dtox(double %double) nounwind { |
| 108 | +; V9-LABEL: dtox: |
| 109 | +; V9: ! %bb.0: |
| 110 | +; V9-NEXT: add %sp, -144, %sp |
| 111 | +; V9-NEXT: std %f0, [%sp+2183] |
| 112 | +; V9-NEXT: ldx [%sp+2183], %o0 |
| 113 | +; V9-NEXT: retl |
| 114 | +; V9-NEXT: add %sp, 144, %sp |
| 115 | +; |
| 116 | +; VIS3-LABEL: dtox: |
| 117 | +; VIS3: ! %bb.0: |
| 118 | +; VIS3-NEXT: retl |
| 119 | +; VIS3-NEXT: movdtox %f0, %o0 |
| 120 | + %x = bitcast double %double to i64 |
| 121 | + ret i64 %x |
| 122 | +} |
| 123 | + |
| 124 | +define double @xtod(i64 %x) nounwind { |
| 125 | +; V9-LABEL: xtod: |
| 126 | +; V9: ! %bb.0: |
| 127 | +; V9-NEXT: add %sp, -144, %sp |
| 128 | +; V9-NEXT: stx %o0, [%sp+2183] |
| 129 | +; V9-NEXT: ldd [%sp+2183], %f0 |
| 130 | +; V9-NEXT: retl |
| 131 | +; V9-NEXT: add %sp, 144, %sp |
| 132 | +; |
| 133 | +; VIS3-LABEL: xtod: |
| 134 | +; VIS3: ! %bb.0: |
| 135 | +; VIS3-NEXT: retl |
| 136 | +; VIS3-NEXT: movxtod %o0, %f0 |
| 137 | + %double = bitcast i64 %x to double |
| 138 | + ret double %double |
| 139 | +} |
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