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[RISCV] Add smcdeleg and ssccfg extensions (#95163)
Specification: https://github.com/riscv/riscv-isa-manual/blob/main/src/smcdeleg.adoc `Ssccfg` introduces one new CSR `scountinhibit`.
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‎clang/test/Preprocessor/riscv-target-features.c

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@@ -27,9 +27,11 @@
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// CHECK-NOT: __riscv_shvstvala {{.*$}}
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// CHECK-NOT: __riscv_shvstvecd {{.*$}}
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// CHECK-NOT: __riscv_smaia {{.*$}}
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// CHECK-NOT: __riscv_smcdeleg {{.*$}}
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// CHECK-NOT: __riscv_smepmp {{.*$}}
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// CHECK-NOT: __riscv_smstateen {{.*$}}
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// CHECK-NOT: __riscv_ssaia {{.*$}}
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// CHECK-NOT: __riscv_ssccfg {{.*$}}
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// CHECK-NOT: __riscv_ssccptr {{.*$}}
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// CHECK-NOT: __riscv_sscofpmf {{.*$}}
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// CHECK-NOT: __riscv_sscounterenw {{.*$}}
@@ -362,6 +364,14 @@
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// RUN: -o - | FileCheck --check-prefix=CHECK-SHVSTVECD-EXT %s
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// CHECK-SHVSTVECD-EXT: __riscv_shvstvecd 1000000{{$}}
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// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32issccfg -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SSCCFG-EXT %s
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// RUN: %clang --target=riscv64-unknown-linux-gnu \
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// RUN: -march=rv64issccfg -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SSCCFG-EXT %s
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// CHECK-SSCCFG-EXT: __riscv_ssccfg 1000000{{$}}
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// RUN: %clang --target=riscv32-unknown-linux-gnu \
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// RUN: -march=rv32issccptr -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SSCCPTR-EXT %s
@@ -1393,6 +1403,14 @@
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// RUN: -o - | FileCheck --check-prefix=CHECK-SSAIA-EXT %s
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// CHECK-SSAIA-EXT: __riscv_ssaia 1000000{{$}}
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// RUN: %clang --target=riscv32 \
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// RUN: -march=rv32ismcdeleg1p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SMCDELEG-EXT %s
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// RUN: %clang --target=riscv64 \
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// RUN: -march=rv64ismcdeleg1p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SMCDELEG-EXT %s
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// CHECK-SMCDELEG-EXT: __riscv_smcdeleg 1000000{{$}}
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// RUN: %clang --target=riscv32 \
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// RUN: -march=rv32ismepmp1p0 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-SMEPMP-EXT %s

‎llvm/docs/RISCVUsage.rst

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@@ -99,9 +99,11 @@ on support follow.
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``Shvstvala`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
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``Shvstvecd`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
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``Smaia`` Supported
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``Smcdeleg`` Supported
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``Smepmp`` Supported
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``Smstateen`` Assembly Support
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``Ssaia`` Supported
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``Ssccfg`` Supported
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``Ssccptr`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
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``Sscofpmf`` Assembly Support
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``Sscounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)

‎llvm/docs/ReleaseNotes.rst

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@@ -157,6 +157,7 @@ Changes to the RISC-V Backend
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* Processors that enable post reg-alloc scheduling (PostMachineScheduler) by default should use the `UsePostRAScheduler` subtarget feature. Setting `PostRAScheduler = 1` in the scheduler model will have no effect on the enabling of the PostMachineScheduler.
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* Zabha is no longer experimental.
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* B (the collection of the Zba, Zbb, Zbs extensions) is supported.
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* Added smcdeleg and ssccfg extensions to -march.
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/RISCVFeatures.td

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@@ -859,6 +859,13 @@ def FeatureStdExtSmepmp
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: RISCVExtension<"smepmp", 1, 0,
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"'Smepmp' (Enhanced Physical Memory Protection)">;
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def FeatureStdExtSmcdeleg
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: RISCVExtension<"smcdeleg", 1, 0,
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"'Smcdeleg' (Counter Delegation Machine Level)">;
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def FeatureStdExtSsccfg
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: RISCVExtension<"ssccfg", 1, 0,
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"'Ssccfg' (Counter Configuration Supervisor Level)">;
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def FeatureStdExtSsccptr
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: RISCVExtension<"ssccptr", 1, 0,
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"'Ssccptr' (Main memory supports page table reads)">;

‎llvm/lib/Target/RISCV/RISCVSystemOperands.td

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@@ -310,6 +310,11 @@ foreach i = 3...31 in {
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def : SysReg<"mhpmevent"#i#"h", !add(0x723, !sub(i, 3))>;
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}
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//===----------------------------------------------------------------------===//
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// Supervisor Counter Setup
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//===----------------------------------------------------------------------===//
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def : SysReg<"scountinhibit", 0x120>;
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//===----------------------------------------------------------------------===//
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// Debug/ Trace Registers (shared with Debug Mode)
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//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/RISCV/attributes.ll

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@@ -42,6 +42,7 @@
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; RUN: llc -mtriple=riscv32 -mattr=+shcounterenw %s -o - | FileCheck --check-prefixes=CHECK,RV32SHCOUNTERENW %s
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; RUN: llc -mtriple=riscv32 -mattr=+shgatpa %s -o - | FileCheck --check-prefixes=CHECK,RV32SHGATPA %s
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; RUN: llc -mtriple=riscv32 -mattr=+shvsatpa %s -o - | FileCheck --check-prefixes=CHECK,RV32SHVSATPA %s
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; RUN: llc -mtriple=riscv32 -mattr=+ssccfg %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCCFG %s
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; RUN: llc -mtriple=riscv32 -mattr=+ssccptr %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCCPTR %s
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; RUN: llc -mtriple=riscv32 -mattr=+sscofpmf %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCOFPMF %s
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; RUN: llc -mtriple=riscv32 -mattr=+sscounterenw %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCOUNTERENW %s
@@ -111,6 +112,7 @@
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; RUN: llc -mtriple=riscv32 -mattr=+zcmop %s -o - | FileCheck --check-prefix=RV32ZCMOP %s
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; RUN: llc -mtriple=riscv32 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SMAIA %s
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; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s
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; RUN: llc -mtriple=riscv32 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCDELEG %s
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; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s
@@ -170,6 +172,7 @@
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; RUN: llc -mtriple=riscv64 -mattr=+shcounterenw %s -o - | FileCheck --check-prefixes=CHECK,RV64SHCOUNTERENW %s
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; RUN: llc -mtriple=riscv64 -mattr=+shgatpa %s -o - | FileCheck --check-prefixes=CHECK,RV64SHGATPA %s
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; RUN: llc -mtriple=riscv64 -mattr=+shvsatpa %s -o - | FileCheck --check-prefixes=CHECK,RV64SHVSATPA %s
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; RUN: llc -mtriple=riscv64 -mattr=+ssccfg %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCCFG %s
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; RUN: llc -mtriple=riscv64 -mattr=+ssccptr %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCCPTR %s
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; RUN: llc -mtriple=riscv64 -mattr=+sscofpmf %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCOFPMF %s
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; RUN: llc -mtriple=riscv64 -mattr=+sscounterenw %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCOUNTERENW %s
@@ -245,6 +248,7 @@
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; RUN: llc -mtriple=riscv64 -mattr=+zcmop %s -o - | FileCheck --check-prefix=RV64ZCMOP %s
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; RUN: llc -mtriple=riscv64 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SMAIA %s
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; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s
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; RUN: llc -mtriple=riscv64 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCDELEG %s
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; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s
@@ -316,6 +320,7 @@
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; RV32SHCOUNTERENW: .attribute 5, "rv32i2p1_shcounterenw1p0"
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; RV32SHGATPA: .attribute 5, "rv32i2p1_shgatpa1p0"
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; RV32SHVSATPA: .attribute 5, "rv32i2p1_shvsatpa1p0"
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; RV32SSCCFG: .attribute 5, "rv32i2p1_ssccfg1p0"
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; RV32SSCCPTR: .attribute 5, "rv32i2p1_ssccptr1p0"
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; RV32SSCOFPMF: .attribute 5, "rv32i2p1_sscofpmf1p0"
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; RV32SSCOUNTERENW: .attribute 5, "rv32i2p1_sscounterenw1p0"
@@ -385,6 +390,7 @@
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; RV32ZCMOP: .attribute 5, "rv32i2p1_zca1p0_zcmop1p0"
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; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0"
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; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
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; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0"
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; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
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; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
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; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"
@@ -447,6 +453,7 @@
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; RV64SHCOUNTERENW: .attribute 5, "rv64i2p1_shcounterenw1p0"
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; RV64SHGATPA: .attribute 5, "rv64i2p1_shgatpa1p0"
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; RV64SHVSATPA: .attribute 5, "rv64i2p1_shvsatpa1p0"
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; RV64SSCCFG: .attribute 5, "rv64i2p1_ssccfg1p0"
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; RV64SSCCPTR: .attribute 5, "rv64i2p1_ssccptr1p0"
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; RV64SSCOFPMF: .attribute 5, "rv64i2p1_sscofpmf1p0"
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; RV64SSCOUNTERENW: .attribute 5, "rv64i2p1_sscounterenw1p0"
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; RV64ZCMOP: .attribute 5, "rv64i2p1_zca1p0_zcmop1p0"
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; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0"
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; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
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; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0"
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; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
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; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"
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; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0"

‎llvm/test/MC/RISCV/attribute-arch.s

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.attribute arch, "rv32i_ssaia1p0"
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# CHECK: attribute 5, "rv32i2p1_ssaia1p0"
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.attribute arch, "rv32i_smcdeleg1p0"
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# CHECK: attribute 5, "rv32i2p1_smcdeleg1p0"
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.attribute arch, "rv32i_smepmp1p0"
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# CHECK: attribute 5, "rv32i2p1_smepmp1p0"
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.attribute arch, "rv32i_ssccfg1p0"
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# CHECK: attribute 5, "rv32i2p1_ssccfg1p0"
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.attribute arch, "rv32i_ssccptr1p0"
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# CHECK: attribute 5, "rv32i2p1_ssccptr1p0"
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‎llvm/test/MC/RISCV/supervisor-csr-names.s

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@@ -369,3 +369,21 @@ csrrs t2, 0x15C, zero
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csrrs t1, stopi, zero
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# uimm12
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csrrs t2, 0xDB0, zero
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#########################################
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# Counter Configuration (Ssccfg)
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#########################################
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# scountinhibit
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# name
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# CHECK-INST: csrrs t1, scountinhibit, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x00,0x12]
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# CHECK-INST-ALIAS: csrr t1, scountinhibit
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# uimm12
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# CHECK-INST: csrrs t2, scountinhibit, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x12]
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# CHECK-INST-ALIAS: csrr t2, scountinhibit
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# name
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csrrs t1, scountinhibit, zero
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# uimm12
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csrrs t2, 0x120, zero

‎llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

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@@ -1009,9 +1009,11 @@ R"(All available -march extensions for RISC-V
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shvstvala 1.0
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shvstvecd 1.0
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smaia 1.0
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smcdeleg 1.0
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smepmp 1.0
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smstateen 1.0
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ssaia 1.0
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ssccfg 1.0
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ssccptr 1.0
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sscofpmf 1.0
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sscounterenw 1.0

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