@@ -2787,85 +2787,68 @@ multiclass sve_fp_fcadd<string asm, SDPatternOperator op> {
2787
2787
// SVE2 Floating Point Convert Group
2788
2788
//===----------------------------------------------------------------------===//
2789
2789
2790
- class sve2_fp_convert_precision<bits<4> opc, string asm,
2791
- ZPRRegOp zprty1, ZPRRegOp zprty2>
2792
- : I<(outs zprty1:$Zd), (ins zprty1:$_Zd, PPR3bAny:$Pg, zprty2:$Zn),
2793
- asm, "\t$Zd, $Pg/m, $Zn",
2790
+ class sve2_fp_convert_precision<bits<4> opc, bit merging, string asm,
2791
+ ZPRRegOp zprty1, ZPRRegOp zprty2, bit destructive=merging>
2792
+ : I<(outs zprty1:$Zd),
2793
+ !if(destructive, (ins zprty1:$_Zd, PPR3bAny:$Pg, zprty2:$Zn),
2794
+ (ins PPR3bAny:$Pg, zprty2:$Zn)),
2795
+ asm, "\t$Zd, " # !if(merging, "$Pg/m", "$Pg/z") # ", $Zn",
2794
2796
"",
2795
2797
[]>, Sched<[]> {
2796
2798
bits<5> Zd;
2797
2799
bits<5> Zn;
2798
2800
bits<3> Pg;
2799
2801
let Inst{31-24} = 0b01100100;
2800
2802
let Inst{23-22} = opc{3-2};
2801
- let Inst{21-18} = 0b0010;
2803
+ let Inst{21-20} = 0b00;
2804
+ let Inst{19} = merging;
2805
+ let Inst{18} = 0b0;
2802
2806
let Inst{17-16} = opc{1-0};
2803
2807
let Inst{15-13} = 0b101;
2804
2808
let Inst{12-10} = Pg;
2805
2809
let Inst{9-5} = Zn;
2806
2810
let Inst{4-0} = Zd;
2807
2811
2808
- let Constraints = "$Zd = $_Zd";
2812
+ let Constraints = !if(destructive, "$Zd = $_Zd", "") ;
2809
2813
let hasSideEffects = 0;
2810
2814
let mayRaiseFPException = 1;
2811
2815
}
2812
2816
2813
2817
multiclass sve2_fp_convert_down_narrow<string asm, string op> {
2814
- def _StoH : sve2_fp_convert_precision<0b1000, asm, ZPR16, ZPR32>;
2815
- def _DtoS : sve2_fp_convert_precision<0b1110, asm, ZPR32, ZPR64>;
2818
+ def _StoH : sve2_fp_convert_precision<0b1000, 0b1, asm, ZPR16, ZPR32>;
2819
+ def _DtoS : sve2_fp_convert_precision<0b1110, 0b1, asm, ZPR32, ZPR64>;
2816
2820
2817
2821
def : SVE_3_Op_Pat<nxv8f16, !cast<SDPatternOperator>(op # _f16f32), nxv8f16, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _StoH)>;
2818
2822
def : SVE_3_Op_Pat<nxv4f32, !cast<SDPatternOperator>(op # _f32f64), nxv4f32, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _DtoS)>;
2819
2823
}
2820
2824
2821
2825
multiclass sve2_fp_convert_up_long<string asm, string op> {
2822
- def _HtoS : sve2_fp_convert_precision<0b1001, asm, ZPR32, ZPR16>;
2823
- def _StoD : sve2_fp_convert_precision<0b1111, asm, ZPR64, ZPR32>;
2826
+ def _HtoS : sve2_fp_convert_precision<0b1001, 0b1, asm, ZPR32, ZPR16>;
2827
+ def _StoD : sve2_fp_convert_precision<0b1111, 0b1, asm, ZPR64, ZPR32>;
2824
2828
2825
2829
def : SVE_3_Op_Pat<nxv4f32, !cast<SDPatternOperator>(op # _f32f16), nxv4f32, nxv4i1, nxv8f16, !cast<Instruction>(NAME # _HtoS)>;
2826
2830
def : SVE_3_Op_Pat<nxv2f64, !cast<SDPatternOperator>(op # _f64f32), nxv2f64, nxv2i1, nxv4f32, !cast<Instruction>(NAME # _StoD)>;
2827
2831
}
2828
2832
2829
2833
multiclass sve2_fp_convert_down_odd_rounding_top<string asm, string op> {
2830
- def _DtoS : sve2_fp_convert_precision<0b0010, asm, ZPR32, ZPR64>;
2834
+ def _DtoS : sve2_fp_convert_precision<0b0010, 0b1, asm, ZPR32, ZPR64>;
2831
2835
2832
2836
def : SVE_3_Op_Pat<nxv4f32, !cast<SDPatternOperator>(op # _f32f64), nxv4f32, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _DtoS)>;
2833
2837
}
2834
2838
2835
- class sve_fp_fcvt2z<bits<4> opc, string asm, ZPRRegOp zprty1,
2836
- ZPRRegOp zprty2>
2837
- : I<(outs zprty1:$Zd), (ins PPR3bAny:$Pg, zprty2:$Zn),
2838
- asm, "\t$Zd, $Pg/z, $Zn",
2839
- "",
2840
- []>, Sched<[]> {
2841
- bits<5> Zd;
2842
- bits<5> Zn;
2843
- bits<3> Pg;
2844
- let Inst{31-24} = 0b01100100;
2845
- let Inst{23-22} = opc{3-2};
2846
- let Inst{21-18} = 0b0000;
2847
- let Inst{17-16} = opc{1-0};
2848
- let Inst{15-13} = 0b101;
2849
- let Inst{12-10} = Pg;
2850
- let Inst{9-5} = Zn;
2851
- let Inst{4-0} = Zd;
2852
- let hasSideEffects = 0;
2853
- let mayRaiseFPException = 1;
2854
- }
2855
-
2856
- multiclass sve_fp_fcvtntz<string asm> {
2857
- def _StoH : sve_fp_fcvt2z<0b1000, asm, ZPR16, ZPR32>;
2858
- def _DtoS : sve_fp_fcvt2z<0b1110, asm, ZPR32, ZPR64>;
2859
- }
2860
-
2861
- multiclass sve_fp_fcvtltz<string asm, string op> {
2862
- def _HtoS : sve_fp_fcvt2z<0b1001, asm, ZPR32, ZPR16>;
2863
- def _StoD : sve_fp_fcvt2z<0b1111, asm, ZPR64, ZPR32>;
2839
+ multiclass sve2_fp_convert_up_long_z<string asm, string op> {
2840
+ def _HtoS : sve2_fp_convert_precision<0b1001, 0b0, asm, ZPR32, ZPR16>;
2841
+ def _StoD : sve2_fp_convert_precision<0b1111, 0b0, asm, ZPR64, ZPR32>;
2864
2842
2865
2843
def : SVE_3_Op_UndefZero_Pat<nxv4f32, !cast<SDPatternOperator>(op # _f32f16), nxv4f32, nxv4i1, nxv8f16, !cast<Instruction>(NAME # _HtoS)>;
2866
2844
def : SVE_3_Op_UndefZero_Pat<nxv2f64, !cast<SDPatternOperator>(op # _f64f32), nxv2f64, nxv2i1, nxv4f32, !cast<Instruction>(NAME # _StoD)>;
2867
2845
}
2868
2846
2847
+ multiclass sve2_fp_convert_down_narrow_z<string asm> {
2848
+ def _StoH : sve2_fp_convert_precision<0b1000, 0b0, asm, ZPR16, ZPR32, /*destructive*/ true>;
2849
+ def _DtoS : sve2_fp_convert_precision<0b1110, 0b0, asm, ZPR32, ZPR64, /*destructive*/ true>;
2850
+ }
2851
+
2869
2852
//===----------------------------------------------------------------------===//
2870
2853
// SVE2 Floating Point Pairwise Group
2871
2854
//===----------------------------------------------------------------------===//
@@ -9311,33 +9294,18 @@ multiclass sve_float_dot_indexed<bit bf, bits<2> opc, ZPRRegOp src1_ty,
9311
9294
def : SVE_4_Op_Imm_Pat<nxv4f32, op, nxv4f32, InVT, InVT, i32, VectorIndexS32b_timm, !cast<Instruction>(NAME)>;
9312
9295
}
9313
9296
9314
- class sve_bfloat_convert<bit N, string asm>
9315
- : I<(outs ZPR16:$Zd), (ins ZPR16:$_Zd, PPR3bAny:$Pg, ZPR32:$Zn),
9316
- asm, "\t$Zd, $Pg/m, $Zn", "", []>, Sched<[]> {
9317
- bits<5> Zd;
9318
- bits<3> Pg;
9319
- bits<5> Zn;
9320
- let Inst{31-25} = 0b0110010;
9321
- let Inst{24} = N;
9322
- let Inst{23-13} = 0b10001010101;
9323
- let Inst{12-10} = Pg;
9324
- let Inst{9-5} = Zn;
9325
- let Inst{4-0} = Zd;
9297
+ multiclass sve_bfloat_convert<string asm, SDPatternOperator op, SDPatternOperator ir_op> {
9298
+ def NAME : sve_fp_2op_p_zd<0b1001010, asm, ZPR32, ZPR16, ElementSizeS>;
9326
9299
9327
- let Constraints = "$Zd = $_Zd";
9328
- let DestructiveInstType = DestructiveOther;
9329
- let ElementSize = ElementSizeS;
9330
- let hasSideEffects = 0;
9331
- let mayRaiseFPException = 1;
9300
+ def : SVE_3_Op_Pat<nxv8bf16, op, nxv8bf16, nxv4i1, nxv4f32, !cast<Instruction>(NAME)>;
9301
+ def : SVE_1_Op_Passthru_Round_Pat<nxv4bf16, ir_op, nxv4i1, nxv4f32, !cast<Instruction>(NAME)>;
9302
+ def : SVE_1_Op_Passthru_Round_Pat<nxv2bf16, ir_op, nxv2i1, nxv2f32, !cast<Instruction>(NAME)>;
9332
9303
}
9333
9304
9334
- multiclass sve_bfloat_convert<bit N, string asm, SDPatternOperator op,
9335
- SDPatternOperator ir_op = null_frag> {
9336
- def NAME : sve_bfloat_convert<N, asm>;
9305
+ multiclass sve_bfloat_convert_top<string asm, SDPatternOperator op> {
9306
+ def NAME : sve2_fp_convert_precision<0b1010, 0b1, asm, ZPR16, ZPR32>;
9337
9307
9338
9308
def : SVE_3_Op_Pat<nxv8bf16, op, nxv8bf16, nxv4i1, nxv4f32, !cast<Instruction>(NAME)>;
9339
- def : SVE_1_Op_Passthru_Round_Pat<nxv4bf16, ir_op, nxv4i1, nxv4f32, !cast<Instruction>(NAME)>;
9340
- def : SVE_1_Op_Passthru_Round_Pat<nxv2bf16, ir_op, nxv2i1, nxv2f32, !cast<Instruction>(NAME)>;
9341
9309
}
9342
9310
9343
9311
//===----------------------------------------------------------------------===//
0 commit comments