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[msan][NFC] Add missing sanitize_memory attribute to arm64-umaxv.ll/arm64-uminv.ll (#129810)
Fixes #129661
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-36
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2 files changed

+148
-36
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‎llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-umaxv.ll

Lines changed: 74 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -14,27 +14,41 @@
1414
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
1515
target triple = "aarch64--linux-android9001"
1616

17-
define i32 @vmax_u8x8(<8 x i8> %a) nounwind ssp {
17+
define i32 @vmax_u8x8(<8 x i8> %a) nounwind ssp #0 {
1818
; CHECK-LABEL: define i32 @vmax_u8x8(
1919
; CHECK-SAME: <8 x i8> [[A:%.*]]) #[[ATTR0:[0-9]+]] {
20-
; CHECK-NEXT: [[ENTRY:.*]]:
20+
; CHECK-NEXT: [[ENTRY:.*:]]
21+
; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i8>, ptr @__msan_param_tls, align 8
2122
; CHECK-NEXT: call void @llvm.donothing()
23+
; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP3]] to i64
24+
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 0
25+
; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB2:.*]], label %[[BB3:.*]], !prof [[PROF1:![0-9]+]]
26+
; CHECK: [[BB2]]:
27+
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4:[0-9]+]]
28+
; CHECK-NEXT: unreachable
29+
; CHECK: [[BB3]]:
2230
; CHECK-NEXT: [[VMAXV_I:%.*]] = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> [[A]]) #[[ATTR3:[0-9]+]]
2331
; CHECK-NEXT: [[TMP:%.*]] = trunc i32 [[VMAXV_I]] to i8
2432
; CHECK-NEXT: [[TMP0:%.*]] = xor i8 [[TMP]], 0
2533
; CHECK-NEXT: [[TMP1:%.*]] = and i8 -1, [[TMP0]]
2634
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i8 [[TMP1]], 0
2735
; CHECK-NEXT: [[_MSPROP_ICMP:%.*]] = and i1 false, [[TMP2]]
2836
; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i8 [[TMP]], 0
37+
; CHECK-NEXT: br i1 [[_MSPROP_ICMP]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]
38+
; CHECK: [[BB7]]:
39+
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
40+
; CHECK-NEXT: unreachable
41+
; CHECK: [[BB8]]:
2942
; CHECK-NEXT: br i1 [[TOBOOL]], label %[[RETURN:.*]], label %[[IF_THEN:.*]]
3043
; CHECK: [[IF_THEN]]:
3144
; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8
3245
; CHECK-NEXT: [[CALL1:%.*]] = tail call i32 @bar() #[[ATTR3]]
3346
; CHECK-NEXT: [[_MSRET:%.*]] = load i32, ptr @__msan_retval_tls, align 8
3447
; CHECK-NEXT: br label %[[RETURN]]
3548
; CHECK: [[RETURN]]:
36-
; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[CALL1]], %[[IF_THEN]] ], [ 0, %[[ENTRY]] ]
37-
; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8
49+
; CHECK-NEXT: [[_MSPHI_S:%.*]] = phi i32 [ [[_MSRET]], %[[IF_THEN]] ], [ 0, %[[BB8]] ]
50+
; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[CALL1]], %[[IF_THEN]] ], [ 0, %[[BB8]] ]
51+
; CHECK-NEXT: store i32 [[_MSPHI_S]], ptr @__msan_retval_tls, align 8
3852
; CHECK-NEXT: ret i32 [[RETVAL_0]]
3953
;
4054
entry:
@@ -54,27 +68,41 @@ return:
5468

5569
declare i32 @bar(...)
5670

57-
define i32 @vmax_u4x16(<4 x i16> %a) nounwind ssp {
71+
define i32 @vmax_u4x16(<4 x i16> %a) nounwind ssp #0 {
5872
; CHECK-LABEL: define i32 @vmax_u4x16(
5973
; CHECK-SAME: <4 x i16> [[A:%.*]]) #[[ATTR0]] {
60-
; CHECK-NEXT: [[ENTRY:.*]]:
74+
; CHECK-NEXT: [[ENTRY:.*:]]
75+
; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 8
6176
; CHECK-NEXT: call void @llvm.donothing()
77+
; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP3]] to i64
78+
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 0
79+
; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB2:.*]], label %[[BB3:.*]], !prof [[PROF1]]
80+
; CHECK: [[BB2]]:
81+
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
82+
; CHECK-NEXT: unreachable
83+
; CHECK: [[BB3]]:
6284
; CHECK-NEXT: [[VMAXV_I:%.*]] = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> [[A]]) #[[ATTR3]]
6385
; CHECK-NEXT: [[TMP:%.*]] = trunc i32 [[VMAXV_I]] to i16
6486
; CHECK-NEXT: [[TMP0:%.*]] = xor i16 [[TMP]], 0
6587
; CHECK-NEXT: [[TMP1:%.*]] = and i16 -1, [[TMP0]]
6688
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i16 [[TMP1]], 0
6789
; CHECK-NEXT: [[_MSPROP_ICMP:%.*]] = and i1 false, [[TMP2]]
6890
; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i16 [[TMP]], 0
91+
; CHECK-NEXT: br i1 [[_MSPROP_ICMP]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]
92+
; CHECK: [[BB7]]:
93+
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
94+
; CHECK-NEXT: unreachable
95+
; CHECK: [[BB8]]:
6996
; CHECK-NEXT: br i1 [[TOBOOL]], label %[[RETURN:.*]], label %[[IF_THEN:.*]]
7097
; CHECK: [[IF_THEN]]:
7198
; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8
7299
; CHECK-NEXT: [[CALL1:%.*]] = tail call i32 @bar() #[[ATTR3]]
73100
; CHECK-NEXT: [[_MSRET:%.*]] = load i32, ptr @__msan_retval_tls, align 8
74101
; CHECK-NEXT: br label %[[RETURN]]
75102
; CHECK: [[RETURN]]:
76-
; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[CALL1]], %[[IF_THEN]] ], [ 0, %[[ENTRY]] ]
77-
; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8
103+
; CHECK-NEXT: [[_MSPHI_S:%.*]] = phi i32 [ [[_MSRET]], %[[IF_THEN]] ], [ 0, %[[BB8]] ]
104+
; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[CALL1]], %[[IF_THEN]] ], [ 0, %[[BB8]] ]
105+
; CHECK-NEXT: store i32 [[_MSPHI_S]], ptr @__msan_retval_tls, align 8
78106
; CHECK-NEXT: ret i32 [[RETVAL_0]]
79107
;
80108
entry:
@@ -92,27 +120,41 @@ return:
92120
ret i32 %retval.0
93121
}
94122

95-
define i32 @vmax_u8x16(<8 x i16> %a) nounwind ssp {
123+
define i32 @vmax_u8x16(<8 x i16> %a) nounwind ssp #0 {
96124
; CHECK-LABEL: define i32 @vmax_u8x16(
97125
; CHECK-SAME: <8 x i16> [[A:%.*]]) #[[ATTR0]] {
98-
; CHECK-NEXT: [[ENTRY:.*]]:
126+
; CHECK-NEXT: [[ENTRY:.*:]]
127+
; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8
99128
; CHECK-NEXT: call void @llvm.donothing()
129+
; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP3]] to i128
130+
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 0
131+
; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB2:.*]], label %[[BB3:.*]], !prof [[PROF1]]
132+
; CHECK: [[BB2]]:
133+
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
134+
; CHECK-NEXT: unreachable
135+
; CHECK: [[BB3]]:
100136
; CHECK-NEXT: [[VMAXV_I:%.*]] = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> [[A]]) #[[ATTR3]]
101137
; CHECK-NEXT: [[TMP:%.*]] = trunc i32 [[VMAXV_I]] to i16
102138
; CHECK-NEXT: [[TMP0:%.*]] = xor i16 [[TMP]], 0
103139
; CHECK-NEXT: [[TMP1:%.*]] = and i16 -1, [[TMP0]]
104140
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i16 [[TMP1]], 0
105141
; CHECK-NEXT: [[_MSPROP_ICMP:%.*]] = and i1 false, [[TMP2]]
106142
; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i16 [[TMP]], 0
143+
; CHECK-NEXT: br i1 [[_MSPROP_ICMP]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]
144+
; CHECK: [[BB7]]:
145+
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
146+
; CHECK-NEXT: unreachable
147+
; CHECK: [[BB8]]:
107148
; CHECK-NEXT: br i1 [[TOBOOL]], label %[[RETURN:.*]], label %[[IF_THEN:.*]]
108149
; CHECK: [[IF_THEN]]:
109150
; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8
110151
; CHECK-NEXT: [[CALL1:%.*]] = tail call i32 @bar() #[[ATTR3]]
111152
; CHECK-NEXT: [[_MSRET:%.*]] = load i32, ptr @__msan_retval_tls, align 8
112153
; CHECK-NEXT: br label %[[RETURN]]
113154
; CHECK: [[RETURN]]:
114-
; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[CALL1]], %[[IF_THEN]] ], [ 0, %[[ENTRY]] ]
115-
; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8
155+
; CHECK-NEXT: [[_MSPHI_S:%.*]] = phi i32 [ [[_MSRET]], %[[IF_THEN]] ], [ 0, %[[BB8]] ]
156+
; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[CALL1]], %[[IF_THEN]] ], [ 0, %[[BB8]] ]
157+
; CHECK-NEXT: store i32 [[_MSPHI_S]], ptr @__msan_retval_tls, align 8
116158
; CHECK-NEXT: ret i32 [[RETVAL_0]]
117159
;
118160
entry:
@@ -130,27 +172,41 @@ return:
130172
ret i32 %retval.0
131173
}
132174

133-
define i32 @vmax_u16x8(<16 x i8> %a) nounwind ssp {
175+
define i32 @vmax_u16x8(<16 x i8> %a) nounwind ssp #0 {
134176
; CHECK-LABEL: define i32 @vmax_u16x8(
135177
; CHECK-SAME: <16 x i8> [[A:%.*]]) #[[ATTR0]] {
136-
; CHECK-NEXT: [[ENTRY:.*]]:
178+
; CHECK-NEXT: [[ENTRY:.*:]]
179+
; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 8
137180
; CHECK-NEXT: call void @llvm.donothing()
181+
; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP3]] to i128
182+
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP4]], 0
183+
; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB2:.*]], label %[[BB3:.*]], !prof [[PROF1]]
184+
; CHECK: [[BB2]]:
185+
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
186+
; CHECK-NEXT: unreachable
187+
; CHECK: [[BB3]]:
138188
; CHECK-NEXT: [[VMAXV_I:%.*]] = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> [[A]]) #[[ATTR3]]
139189
; CHECK-NEXT: [[TMP:%.*]] = trunc i32 [[VMAXV_I]] to i8
140190
; CHECK-NEXT: [[TMP0:%.*]] = xor i8 [[TMP]], 0
141191
; CHECK-NEXT: [[TMP1:%.*]] = and i8 -1, [[TMP0]]
142192
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i8 [[TMP1]], 0
143193
; CHECK-NEXT: [[_MSPROP_ICMP:%.*]] = and i1 false, [[TMP2]]
144194
; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i8 [[TMP]], 0
195+
; CHECK-NEXT: br i1 [[_MSPROP_ICMP]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]
196+
; CHECK: [[BB7]]:
197+
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
198+
; CHECK-NEXT: unreachable
199+
; CHECK: [[BB8]]:
145200
; CHECK-NEXT: br i1 [[TOBOOL]], label %[[RETURN:.*]], label %[[IF_THEN:.*]]
146201
; CHECK: [[IF_THEN]]:
147202
; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8
148203
; CHECK-NEXT: [[CALL1:%.*]] = tail call i32 @bar() #[[ATTR3]]
149204
; CHECK-NEXT: [[_MSRET:%.*]] = load i32, ptr @__msan_retval_tls, align 8
150205
; CHECK-NEXT: br label %[[RETURN]]
151206
; CHECK: [[RETURN]]:
152-
; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[CALL1]], %[[IF_THEN]] ], [ 0, %[[ENTRY]] ]
153-
; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8
207+
; CHECK-NEXT: [[_MSPHI_S:%.*]] = phi i32 [ [[_MSRET]], %[[IF_THEN]] ], [ 0, %[[BB8]] ]
208+
; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[CALL1]], %[[IF_THEN]] ], [ 0, %[[BB8]] ]
209+
; CHECK-NEXT: store i32 [[_MSPHI_S]], ptr @__msan_retval_tls, align 8
154210
; CHECK-NEXT: ret i32 [[RETVAL_0]]
155211
;
156212
entry:
@@ -177,9 +233,9 @@ define <8 x i8> @test_vmaxv_u8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) #0 {
177233
; CHECK-NEXT: call void @llvm.donothing()
178234
; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to i64
179235
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
180-
; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1:![0-9]+]]
236+
; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]
181237
; CHECK: [[BB3]]:
182-
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4:[0-9]+]]
238+
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
183239
; CHECK-NEXT: unreachable
184240
; CHECK: [[BB4]]:
185241
; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> [[A2]])

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