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[RISCV] Add coverage for int reductions of <3 x i8> vectors
Specifically, to illustrate our general lowering strategy for non-power of two vectors.
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‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll

Lines changed: 171 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,24 @@ define i8 @vreduce_add_v2i8(ptr %x) {
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ret i8 %red
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}
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declare i8 @llvm.vector.reduce.add.v3i8(<3 x i8>)
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define i8 @vreduce_add_v3i8(ptr %x) {
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; CHECK-LABEL: vreduce_add_v3i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vmv.s.x v9, zero
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vslideup.vi v8, v9, 3
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; CHECK-NEXT: vredsum.vs v8, v8, v9
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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%v = load <3 x i8>, ptr %x
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%red = call i8 @llvm.vector.reduce.add.v3i8(<3 x i8> %v)
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ret i8 %red
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}
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declare i8 @llvm.vector.reduce.add.v4i8(<4 x i8>)
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define i8 @vreduce_add_v4i8(ptr %x) {
@@ -1743,6 +1761,25 @@ define i8 @vreduce_and_v2i8(ptr %x) {
17431761
ret i8 %red
17441762
}
17451763

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declare i8 @llvm.vector.reduce.and.v3i8(<3 x i8>)
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define i8 @vreduce_and_v3i8(ptr %x) {
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; CHECK-LABEL: vreduce_and_v3i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vmv.v.i v9, -1
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; CHECK-NEXT: vslideup.vi v8, v9, 3
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; CHECK-NEXT: vredand.vs v8, v8, v8
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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%v = load <3 x i8>, ptr %x
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%red = call i8 @llvm.vector.reduce.and.v3i8(<3 x i8> %v)
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ret i8 %red
1780+
}
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17461783
declare i8 @llvm.vector.reduce.and.v4i8(<4 x i8>)
17471784

17481785
define i8 @vreduce_and_v4i8(ptr %x) {
@@ -2328,6 +2365,24 @@ define i8 @vreduce_or_v2i8(ptr %x) {
23282365
ret i8 %red
23292366
}
23302367

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declare i8 @llvm.vector.reduce.or.v3i8(<3 x i8>)
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define i8 @vreduce_or_v3i8(ptr %x) {
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; CHECK-LABEL: vreduce_or_v3i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vmv.s.x v9, zero
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vslideup.vi v8, v9, 3
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; CHECK-NEXT: vredor.vs v8, v8, v8
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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%v = load <3 x i8>, ptr %x
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%red = call i8 @llvm.vector.reduce.or.v3i8(<3 x i8> %v)
2383+
ret i8 %red
2384+
}
2385+
23312386
declare i8 @llvm.vector.reduce.or.v4i8(<4 x i8>)
23322387

23332388
define i8 @vreduce_or_v4i8(ptr %x) {
@@ -2914,6 +2969,24 @@ define i8 @vreduce_xor_v2i8(ptr %x) {
29142969
ret i8 %red
29152970
}
29162971

2972+
declare i8 @llvm.vector.reduce.xor.v3i8(<3 x i8>)
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2974+
define i8 @vreduce_xor_v3i8(ptr %x) {
2975+
; CHECK-LABEL: vreduce_xor_v3i8:
2976+
; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
2979+
; CHECK-NEXT: vmv.s.x v9, zero
2980+
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
2981+
; CHECK-NEXT: vslideup.vi v8, v9, 3
2982+
; CHECK-NEXT: vredxor.vs v8, v8, v9
2983+
; CHECK-NEXT: vmv.x.s a0, v8
2984+
; CHECK-NEXT: ret
2985+
%v = load <3 x i8>, ptr %x
2986+
%red = call i8 @llvm.vector.reduce.xor.v3i8(<3 x i8> %v)
2987+
ret i8 %red
2988+
}
2989+
29172990
declare i8 @llvm.vector.reduce.xor.v4i8(<4 x i8>)
29182991

29192992
define i8 @vreduce_xor_v4i8(ptr %x) {
@@ -3531,6 +3604,25 @@ define i8 @vreduce_smin_v2i8(ptr %x) {
35313604
ret i8 %red
35323605
}
35333606

3607+
declare i8 @llvm.vector.reduce.smin.v3i8(<3 x i8>)
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3609+
define i8 @vreduce_smin_v3i8(ptr %x) {
3610+
; CHECK-LABEL: vreduce_smin_v3i8:
3611+
; CHECK: # %bb.0:
3612+
; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma
3613+
; CHECK-NEXT: vle8.v v8, (a0)
3614+
; CHECK-NEXT: li a0, 127
3615+
; CHECK-NEXT: vmv.s.x v9, a0
3616+
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vslideup.vi v8, v9, 3
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; CHECK-NEXT: vredmin.vs v8, v8, v8
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
3621+
%v = load <3 x i8>, ptr %x
3622+
%red = call i8 @llvm.vector.reduce.smin.v3i8(<3 x i8> %v)
3623+
ret i8 %red
3624+
}
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35343626
declare i8 @llvm.vector.reduce.smin.v4i8(<4 x i8>)
35353627

35363628
define i8 @vreduce_smin_v4i8(ptr %x) {
@@ -4116,6 +4208,25 @@ define i8 @vreduce_smax_v2i8(ptr %x) {
41164208
ret i8 %red
41174209
}
41184210

4211+
declare i8 @llvm.vector.reduce.smax.v3i8(<3 x i8>)
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4213+
define i8 @vreduce_smax_v3i8(ptr %x) {
4214+
; CHECK-LABEL: vreduce_smax_v3i8:
4215+
; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: li a0, -128
4219+
; CHECK-NEXT: vmv.s.x v9, a0
4220+
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
4221+
; CHECK-NEXT: vslideup.vi v8, v9, 3
4222+
; CHECK-NEXT: vredmax.vs v8, v8, v8
4223+
; CHECK-NEXT: vmv.x.s a0, v8
4224+
; CHECK-NEXT: ret
4225+
%v = load <3 x i8>, ptr %x
4226+
%red = call i8 @llvm.vector.reduce.smax.v3i8(<3 x i8> %v)
4227+
ret i8 %red
4228+
}
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41194230
declare i8 @llvm.vector.reduce.smax.v4i8(<4 x i8>)
41204231

41214232
define i8 @vreduce_smax_v4i8(ptr %x) {
@@ -4701,6 +4812,24 @@ define i8 @vreduce_umin_v2i8(ptr %x) {
47014812
ret i8 %red
47024813
}
47034814

4815+
declare i8 @llvm.vector.reduce.umin.v3i8(<3 x i8>)
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4817+
define i8 @vreduce_umin_v3i8(ptr %x) {
4818+
; CHECK-LABEL: vreduce_umin_v3i8:
4819+
; CHECK: # %bb.0:
4820+
; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vmv.v.i v9, -1
4824+
; CHECK-NEXT: vslideup.vi v8, v9, 3
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; CHECK-NEXT: vredminu.vs v8, v8, v8
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; CHECK-NEXT: vmv.x.s a0, v8
4827+
; CHECK-NEXT: ret
4828+
%v = load <3 x i8>, ptr %x
4829+
%red = call i8 @llvm.vector.reduce.umin.v3i8(<3 x i8> %v)
4830+
ret i8 %red
4831+
}
4832+
47044833
declare i8 @llvm.vector.reduce.umin.v4i8(<4 x i8>)
47054834

47064835
define i8 @vreduce_umin_v4i8(ptr %x) {
@@ -5286,6 +5415,24 @@ define i8 @vreduce_umax_v2i8(ptr %x) {
52865415
ret i8 %red
52875416
}
52885417

5418+
declare i8 @llvm.vector.reduce.umax.v3i8(<3 x i8>)
5419+
5420+
define i8 @vreduce_umax_v3i8(ptr %x) {
5421+
; CHECK-LABEL: vreduce_umax_v3i8:
5422+
; CHECK: # %bb.0:
5423+
; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma
5424+
; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vmv.s.x v9, zero
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
5427+
; CHECK-NEXT: vslideup.vi v8, v9, 3
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; CHECK-NEXT: vredmaxu.vs v8, v8, v8
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
5431+
%v = load <3 x i8>, ptr %x
5432+
%red = call i8 @llvm.vector.reduce.umax.v3i8(<3 x i8> %v)
5433+
ret i8 %red
5434+
}
5435+
52895436
declare i8 @llvm.vector.reduce.umax.v4i8(<4 x i8>)
52905437

52915438
define i8 @vreduce_umax_v4i8(ptr %x) {
@@ -5872,6 +6019,30 @@ define i8 @vreduce_mul_v2i8(ptr %x) {
58726019
ret i8 %red
58736020
}
58746021

6022+
declare i8 @llvm.vector.reduce.mul.v3i8(<3 x i8>)
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6024+
define i8 @vreduce_mul_v3i8(ptr %x) {
6025+
; CHECK-LABEL: vreduce_mul_v3i8:
6026+
; CHECK: # %bb.0:
6027+
; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma
6028+
; CHECK-NEXT: vle8.v v8, (a0)
6029+
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vmv.v.i v9, 1
6031+
; CHECK-NEXT: vslideup.vi v8, v9, 3
6032+
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
6033+
; CHECK-NEXT: vslidedown.vi v9, v8, 2
6034+
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
6035+
; CHECK-NEXT: vmul.vv v8, v8, v9
6036+
; CHECK-NEXT: vslidedown.vi v9, v8, 1
6037+
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
6038+
; CHECK-NEXT: vmul.vv v8, v8, v9
6039+
; CHECK-NEXT: vmv.x.s a0, v8
6040+
; CHECK-NEXT: ret
6041+
%v = load <3 x i8>, ptr %x
6042+
%red = call i8 @llvm.vector.reduce.mul.v3i8(<3 x i8> %v)
6043+
ret i8 %red
6044+
}
6045+
58756046
declare i8 @llvm.vector.reduce.mul.v4i8(<4 x i8>)
58766047

58776048
define i8 @vreduce_mul_v4i8(ptr %x) {

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