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arsenmarsenm
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AtomicExpand: Emit or with constant on RHS
This will save later code from commuting it.
1 parent dadf6f2 commit 31af5e9

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8 files changed

+75
-75
lines changed

8 files changed

+75
-75
lines changed

‎llvm/lib/CodeGen/AtomicExpandPass.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -943,7 +943,7 @@ AtomicRMWInst *AtomicExpandImpl::widenPartwordAtomicRMW(AtomicRMWInst *AI) {
943943

944944
if (Op == AtomicRMWInst::And)
945945
NewOperand =
946-
Builder.CreateOr(PMV.Inv_Mask, ValOperand_Shifted, "AndOperand");
946+
Builder.CreateOr(ValOperand_Shifted, PMV.Inv_Mask, "AndOperand");
947947
else
948948
NewOperand = ValOperand_Shifted;
949949

‎llvm/test/CodeGen/RISCV/atomic-rmw.ll

Lines changed: 54 additions & 54 deletions
Large diffs are not rendered by default.

‎llvm/test/CodeGen/RISCV/atomic-signext.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -362,7 +362,7 @@ define signext i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind {
362362
; RV32IA-NEXT: not a3, a3
363363
; RV32IA-NEXT: andi a1, a1, 255
364364
; RV32IA-NEXT: sll a1, a1, a0
365-
; RV32IA-NEXT: or a1, a3, a1
365+
; RV32IA-NEXT: or a1, a1, a3
366366
; RV32IA-NEXT: amoand.w a1, a1, (a2)
367367
; RV32IA-NEXT: srl a0, a1, a0
368368
; RV32IA-NEXT: slli a0, a0, 24
@@ -390,7 +390,7 @@ define signext i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind {
390390
; RV64IA-NEXT: not a3, a3
391391
; RV64IA-NEXT: andi a1, a1, 255
392392
; RV64IA-NEXT: sllw a1, a1, a0
393-
; RV64IA-NEXT: or a1, a3, a1
393+
; RV64IA-NEXT: or a1, a1, a3
394394
; RV64IA-NEXT: amoand.w a1, a1, (a2)
395395
; RV64IA-NEXT: srlw a0, a1, a0
396396
; RV64IA-NEXT: slli a0, a0, 56
@@ -1403,7 +1403,7 @@ define signext i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind {
14031403
; RV32IA-NEXT: not a4, a4
14041404
; RV32IA-NEXT: and a1, a1, a3
14051405
; RV32IA-NEXT: sll a1, a1, a0
1406-
; RV32IA-NEXT: or a1, a4, a1
1406+
; RV32IA-NEXT: or a1, a1, a4
14071407
; RV32IA-NEXT: amoand.w a1, a1, (a2)
14081408
; RV32IA-NEXT: srl a0, a1, a0
14091409
; RV32IA-NEXT: slli a0, a0, 16
@@ -1432,7 +1432,7 @@ define signext i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind {
14321432
; RV64IA-NEXT: not a4, a4
14331433
; RV64IA-NEXT: and a1, a1, a3
14341434
; RV64IA-NEXT: sllw a1, a1, a0
1435-
; RV64IA-NEXT: or a1, a4, a1
1435+
; RV64IA-NEXT: or a1, a1, a4
14361436
; RV64IA-NEXT: amoand.w a1, a1, (a2)
14371437
; RV64IA-NEXT: srlw a0, a1, a0
14381438
; RV64IA-NEXT: slli a0, a0, 48

‎llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16-system.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -152,7 +152,7 @@ define i16 @test_atomicrmw_and_i16_global_system(ptr addrspace(1) %ptr, i16 %val
152152
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
153153
; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VALUE:%.*]] to i32
154154
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
155-
; CHECK-NEXT: [[ANDOPERAND:%.*]] = or i32 [[INV_MASK]], [[VALOPERAND_SHIFTED]]
155+
; CHECK-NEXT: [[ANDOPERAND:%.*]] = or i32 [[VALOPERAND_SHIFTED]], [[INV_MASK]]
156156
; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw and ptr addrspace(1) [[ALIGNEDADDR]], i32 [[ANDOPERAND]] seq_cst, align 4
157157
; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP4]], [[SHIFTAMT]]
158158
; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16

‎llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -153,7 +153,7 @@ define i16 @test_atomicrmw_and_i16_global_agent(ptr addrspace(1) %ptr, i16 %valu
153153
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
154154
; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VALUE:%.*]] to i32
155155
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
156-
; CHECK-NEXT: [[ANDOPERAND:%.*]] = or i32 [[INV_MASK]], [[VALOPERAND_SHIFTED]]
156+
; CHECK-NEXT: [[ANDOPERAND:%.*]] = or i32 [[VALOPERAND_SHIFTED]], [[INV_MASK]]
157157
; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw and ptr addrspace(1) [[ALIGNEDADDR]], i32 [[ANDOPERAND]] syncscope("agent") seq_cst, align 4
158158
; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP4]], [[SHIFTAMT]]
159159
; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16

‎llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8-system.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -161,7 +161,7 @@ define i8 @test_atomicrmw_and_i8_global_system(ptr addrspace(1) %ptr, i8 %value)
161161
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
162162
; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[VALUE:%.*]] to i32
163163
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
164-
; CHECK-NEXT: [[ANDOPERAND:%.*]] = or i32 [[INV_MASK]], [[VALOPERAND_SHIFTED]]
164+
; CHECK-NEXT: [[ANDOPERAND:%.*]] = or i32 [[VALOPERAND_SHIFTED]], [[INV_MASK]]
165165
; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw and ptr addrspace(1) [[ALIGNEDADDR]], i32 [[ANDOPERAND]] seq_cst, align 4
166166
; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP4]], [[SHIFTAMT]]
167167
; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i8

‎llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -264,7 +264,7 @@ define i8 @test_atomicrmw_and_i8_global_agent(ptr addrspace(1) %ptr, i8 %value)
264264
; GCN-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
265265
; GCN-NEXT: [[TMP3:%.*]] = zext i8 [[VALUE:%.*]] to i32
266266
; GCN-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
267-
; GCN-NEXT: [[ANDOPERAND:%.*]] = or i32 [[INV_MASK]], [[VALOPERAND_SHIFTED]]
267+
; GCN-NEXT: [[ANDOPERAND:%.*]] = or i32 [[VALOPERAND_SHIFTED]], [[INV_MASK]]
268268
; GCN-NEXT: [[TMP4:%.*]] = atomicrmw and ptr addrspace(1) [[ALIGNEDADDR]], i32 [[ANDOPERAND]] syncscope("agent") seq_cst, align 4
269269
; GCN-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP4]], [[SHIFTAMT]]
270270
; GCN-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i8
@@ -279,7 +279,7 @@ define i8 @test_atomicrmw_and_i8_global_agent(ptr addrspace(1) %ptr, i8 %value)
279279
; R600-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
280280
; R600-NEXT: [[TMP3:%.*]] = zext i8 [[VALUE:%.*]] to i32
281281
; R600-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[TMP2]]
282-
; R600-NEXT: [[ANDOPERAND:%.*]] = or i32 [[INV_MASK]], [[VALOPERAND_SHIFTED]]
282+
; R600-NEXT: [[ANDOPERAND:%.*]] = or i32 [[VALOPERAND_SHIFTED]], [[INV_MASK]]
283283
; R600-NEXT: [[TMP4:%.*]] = atomicrmw and ptr addrspace(1) [[ALIGNEDADDR]], i32 [[ANDOPERAND]] syncscope("agent") seq_cst, align 4
284284
; R600-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP4]], [[TMP2]]
285285
; R600-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i8

‎llvm/test/Transforms/AtomicExpand/SPARC/partword.ll

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -220,7 +220,7 @@ define i16 @test_and_i16(ptr %arg, i16 %val) {
220220
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
221221
; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VAL:%.*]] to i32
222222
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
223-
; CHECK-NEXT: [[ANDOPERAND:%.*]] = or i32 [[INV_MASK]], [[VALOPERAND_SHIFTED]]
223+
; CHECK-NEXT: [[ANDOPERAND:%.*]] = or i32 [[VALOPERAND_SHIFTED]], [[INV_MASK]]
224224
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4
225225
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
226226
; CHECK: atomicrmw.start:
@@ -262,18 +262,18 @@ define i16 @test_min_i16(ptr %arg, i16 %val) {
262262
; CHECK-NEXT: [[TMP4:%.*]] = icmp sle i16 [[EXTRACTED]], [[VAL:%.*]]
263263
; CHECK-NEXT: [[NEW:%.*]] = select i1 [[TMP4]], i16 [[EXTRACTED]], i16 [[VAL]]
264264
; CHECK-NEXT: [[EXTENDED:%.*]] = zext i16 [[NEW]] to i32
265-
; CHECK-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
265+
; CHECK-NEXT: [[SHIFTED1:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
266266
; CHECK-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
267-
; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
267+
; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED1]]
268268
; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] monotonic monotonic, align 4
269269
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
270270
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0
271271
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
272272
; CHECK: atomicrmw.end:
273-
; CHECK-NEXT: [[SHIFTED3:%.*]] = lshr i32 [[NEWLOADED]], [[SHIFTAMT]]
274-
; CHECK-NEXT: [[EXTRACTED4:%.*]] = trunc i32 [[SHIFTED3]] to i16
273+
; CHECK-NEXT: [[SHIFTED2:%.*]] = lshr i32 [[NEWLOADED]], [[SHIFTAMT]]
274+
; CHECK-NEXT: [[EXTRACTED3:%.*]] = trunc i32 [[SHIFTED2]] to i16
275275
; CHECK-NEXT: fence seq_cst
276-
; CHECK-NEXT: ret i16 [[EXTRACTED4]]
276+
; CHECK-NEXT: ret i16 [[EXTRACTED3]]
277277
;
278278
entry:
279279
%ret = atomicrmw min ptr %arg, i16 %val seq_cst
@@ -301,17 +301,17 @@ define half @test_atomicrmw_fadd_f16(ptr %ptr, half %value) {
301301
; CHECK-NEXT: [[NEW:%.*]] = fadd half [[TMP5]], [[VALUE:%.*]]
302302
; CHECK-NEXT: [[TMP6:%.*]] = bitcast half [[NEW]] to i16
303303
; CHECK-NEXT: [[EXTENDED:%.*]] = zext i16 [[TMP6]] to i32
304-
; CHECK-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
304+
; CHECK-NEXT: [[SHIFTED1:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
305305
; CHECK-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
306-
; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
306+
; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED1]]
307307
; CHECK-NEXT: [[TMP7:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] monotonic monotonic, align 4
308308
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1
309309
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0
310310
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
311311
; CHECK: atomicrmw.end:
312-
; CHECK-NEXT: [[SHIFTED3:%.*]] = lshr i32 [[NEWLOADED]], [[SHIFTAMT]]
313-
; CHECK-NEXT: [[EXTRACTED4:%.*]] = trunc i32 [[SHIFTED3]] to i16
314-
; CHECK-NEXT: [[TMP8:%.*]] = bitcast i16 [[EXTRACTED4]] to half
312+
; CHECK-NEXT: [[SHIFTED2:%.*]] = lshr i32 [[NEWLOADED]], [[SHIFTAMT]]
313+
; CHECK-NEXT: [[EXTRACTED3:%.*]] = trunc i32 [[SHIFTED2]] to i16
314+
; CHECK-NEXT: [[TMP8:%.*]] = bitcast i16 [[EXTRACTED3]] to half
315315
; CHECK-NEXT: fence seq_cst
316316
; CHECK-NEXT: ret half [[TMP8]]
317317
;

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