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[RISCV] Use TableGen-based macro fusion
We convert LUIADDI macro fusion to TableGen. For test, I added `MacroFusions` to `SiFive7Model`.
1 parent f4cd61c commit 31d8a99

13 files changed

+44
-121
lines changed

‎llvm/lib/Target/RISCV/CMakeLists.txt

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@ set(LLVM_TARGET_DEFINITIONS RISCV.td)
55
tablegen(LLVM RISCVGenAsmMatcher.inc -gen-asm-matcher)
66
tablegen(LLVM RISCVGenAsmWriter.inc -gen-asm-writer)
77
tablegen(LLVM RISCVGenCompressInstEmitter.inc -gen-compress-inst-emitter)
8+
tablegen(LLVM RISCVGenMacroFusion.inc -gen-macro-fusion-pred)
89
tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
910
tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler)
1011
tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
@@ -43,7 +44,6 @@ add_llvm_target(RISCVCodeGen
4344
RISCVISelDAGToDAG.cpp
4445
RISCVISelLowering.cpp
4546
RISCVMachineFunctionInfo.cpp
46-
RISCVMacroFusion.cpp
4747
RISCVMergeBaseOffset.cpp
4848
RISCVOptWInstrs.cpp
4949
RISCVPostRAExpandPseudoInsts.cpp

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,9 @@ std::unique_ptr<MCObjectTargetWriter> createRISCVELFObjectWriter(uint8_t OSABI,
4848
#define GET_INSTRINFO_MC_HELPER_DECLS
4949
#include "RISCVGenInstrInfo.inc"
5050

51+
#define GET_MACRO_FUSION_ENUM
52+
#include "RISCVGenMacroFusion.inc"
53+
5154
#define GET_SUBTARGETINFO_ENUM
5255
#include "RISCVGenSubtargetInfo.inc"
5356

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -236,7 +236,7 @@ InstSeq generateInstSeq(int64_t Val, const MCSubtargetInfo &STI) {
236236
// NOTE: We don't check for C extension to minimize differences in generated
237237
// code.
238238
bool IsShiftedCompressible =
239-
isInt<6>(ShiftedVal) && !STI.hasFeature(RISCV::TuneLUIADDIFusion);
239+
isInt<6>(ShiftedVal) && !STI.hasMacroFusion(RISCV::LUIADDI);
240240
RISCVMatInt::InstSeq TmpSeq;
241241
generateInstSeqImpl(ShiftedVal, STI, TmpSeq);
242242

‎llvm/lib/Target/RISCV/RISCV.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,7 @@ include "GISel/RISCVRegisterBanks.td"
3434
// RISC-V Scheduling Models
3535
//===----------------------------------------------------------------------===//
3636

37+
include "RISCVMacroFusion.td"
3738
include "RISCVSchedRocket.td"
3839
include "RISCVSchedSiFive7.td"
3940
include "RISCVSchedSyntacoreSCR1.td"

‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -971,10 +971,6 @@ def TuneDLenFactor2
971971
: SubtargetFeature<"dlen-factor-2", "DLenFactor2", "true",
972972
"Vector unit DLEN(data path width) is half of VLEN">;
973973

974-
def TuneLUIADDIFusion
975-
: SubtargetFeature<"lui-addi-fusion", "HasLUIADDIFusion",
976-
"true", "Enable LUI+ADDI macrofusion">;
977-
978974
def TuneNoDefaultUnroll
979975
: SubtargetFeature<"no-default-unroll", "EnableDefaultUnroll", "false",
980976
"Disable default unroll preference.">;
@@ -993,8 +989,7 @@ def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
993989
TuneShortForwardBranchOpt]>;
994990

995991
def TuneVentanaVeyron : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron",
996-
"Ventana-Veyron Series processors",
997-
[TuneLUIADDIFusion]>;
992+
"Ventana-Veyron Series processors">;
998993

999994
// Assume that lock-free native-width atomics are available, even if the target
1000995
// and operating system combination would not usually provide them. The user

‎llvm/lib/Target/RISCV/RISCVMacroFusion.cpp

Lines changed: 0 additions & 69 deletions
This file was deleted.

‎llvm/lib/Target/RISCV/RISCVMacroFusion.h

Lines changed: 0 additions & 28 deletions
This file was deleted.

‎llvm/lib/Target/RISCV/RISCVMacroFusion.td

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
//==----- RISCVMacroFusion.td - Macro Fusion Definitions -----*- tablegen -*-=//
2+
//
3+
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
// See https://llvm.org/LICENSE.txt for license information.
5+
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
//
7+
//===----------------------------------------------------------------------===//
8+
9+
// ===---------------------------------------------------------------------===//
10+
// The following definitions describe the macro fusion predicators.
11+
12+
def LUIADDI: SimpleFusion<CheckOpcode<[LUI]>, CheckOpcode<[ADDI, ADDIW]>>;

‎llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -200,6 +200,7 @@ def SiFive7Model : SchedMachineModel {
200200
HasStdExtZcmt, HasStdExtZknd, HasStdExtZkne,
201201
HasStdExtZknh, HasStdExtZksed, HasStdExtZksh,
202202
HasStdExtZkr];
203+
let MacroFusions = [LUIADDI];
203204
}
204205

205206
// The SiFive7 microarchitecture has three pipelines: A, B, V.

‎llvm/lib/Target/RISCV/RISCVSubtarget.cpp

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -16,8 +16,9 @@
1616
#include "GISel/RISCVRegisterBankInfo.h"
1717
#include "RISCV.h"
1818
#include "RISCVFrameLowering.h"
19-
#include "RISCVMacroFusion.h"
2019
#include "RISCVTargetMachine.h"
20+
#include "llvm/CodeGen/MacroFusion.h"
21+
#include "llvm/CodeGen/ScheduleDAGMutation.h"
2122
#include "llvm/MC/TargetRegistry.h"
2223
#include "llvm/Support/ErrorHandling.h"
2324

@@ -29,11 +30,16 @@ using namespace llvm;
2930
#define GET_SUBTARGETINFO_CTOR
3031
#include "RISCVGenSubtargetInfo.inc"
3132

32-
namespace llvm::RISCVTuneInfoTable {
33+
namespace llvm {
34+
#define GET_RISCV_MACRO_FUSION_PRED_IMPL
35+
#include "RISCVGenMacroFusion.inc"
36+
37+
namespace RISCVTuneInfoTable {
3338

3439
#define GET_RISCVTuneInfoTable_IMPL
3540
#include "RISCVGenSearchableTables.inc"
36-
} // namespace llvm::RISCVTuneInfoTable
41+
} // namespace RISCVTuneInfoTable
42+
} // namespace llvm
3743

3844
static cl::opt<bool> EnableSubRegLiveness("riscv-enable-subreg-liveness",
3945
cl::init(true), cl::Hidden);
@@ -183,7 +189,7 @@ bool RISCVSubtarget::enableSubRegLiveness() const {
183189

184190
void RISCVSubtarget::getPostRAMutations(
185191
std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
186-
Mutations.push_back(createRISCVMacroFusionDAGMutation());
192+
Mutations.push_back(createMacroFusionDAGMutation(getMacroFusions()));
187193
}
188194

189195
/// Enable use of alias analysis during code generation (during MI

‎llvm/lib/Target/RISCV/RISCVSubtarget.h

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,9 @@ struct RISCVTuneInfo {
5050
#include "RISCVGenSearchableTables.inc"
5151
} // namespace RISCVTuneInfoTable
5252

53+
#define GET_RISCV_MACRO_FUSION_PRED_DECL
54+
#include "RISCVGenMacroFusion.inc"
55+
5356
class RISCVSubtarget : public RISCVGenSubtargetInfo {
5457
public:
5558
// clang-format off
@@ -190,8 +193,6 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
190193
return UserReservedRegister[i];
191194
}
192195

193-
bool hasMacroFusion() const { return hasLUIADDIFusion(); }
194-
195196
// Vector codegen related methods.
196197
bool hasVInstructions() const { return HasStdExtZve32x; }
197198
bool hasVInstructionsI64() const { return HasStdExtZve64x; }

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,6 @@
1414
#include "MCTargetDesc/RISCVBaseInfo.h"
1515
#include "RISCV.h"
1616
#include "RISCVMachineFunctionInfo.h"
17-
#include "RISCVMacroFusion.h"
1817
#include "RISCVTargetObjectFile.h"
1918
#include "RISCVTargetTransformInfo.h"
2019
#include "TargetInfo/RISCVTargetInfo.h"
@@ -26,6 +25,8 @@
2625
#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
2726
#include "llvm/CodeGen/MIRParser/MIParser.h"
2827
#include "llvm/CodeGen/MIRYamlMapping.h"
28+
#include "llvm/CodeGen/MachineScheduler.h"
29+
#include "llvm/CodeGen/MacroFusion.h"
2930
#include "llvm/CodeGen/Passes.h"
3031
#include "llvm/CodeGen/RegAllocRegistry.h"
3132
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
@@ -345,9 +346,9 @@ class RISCVPassConfig : public TargetPassConfig {
345346
ScheduleDAGInstrs *
346347
createMachineScheduler(MachineSchedContext *C) const override {
347348
const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
348-
if (ST.hasMacroFusion()) {
349+
if (ST.enableMacroFusion()) {
349350
ScheduleDAGMILive *DAG = createGenericSchedLive(C);
350-
DAG->addMutation(createRISCVMacroFusionDAGMutation());
351+
DAG->addMutation(createMacroFusionDAGMutation(ST.getMacroFusions()));
351352
return DAG;
352353
}
353354
return nullptr;
@@ -356,9 +357,9 @@ class RISCVPassConfig : public TargetPassConfig {
356357
ScheduleDAGInstrs *
357358
createPostMachineScheduler(MachineSchedContext *C) const override {
358359
const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
359-
if (ST.hasMacroFusion()) {
360+
if (ST.enableMacroFusion()) {
360361
ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
361-
DAG->addMutation(createRISCVMacroFusionDAGMutation());
362+
DAG->addMutation(createMacroFusionDAGMutation(ST.getMacroFusions()));
362363
return DAG;
363364
}
364365
return nullptr;

‎llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
;RUN: llc < %s -mtriple=riscv64 -mattr=+f -mcpu=sifive-u74 -target-abi=lp64f \
2+
;RUN: llc < %s -mtriple=riscv64 -mattr=+f -mcpu=sifive-u74 -misched-fusion=false -target-abi=lp64f \
33
;RUN: | FileCheck %s --check-prefix=NOFUSION
4-
;RUN: llc < %s -mtriple=riscv64 -mattr=+f,+lui-addi-fusion -mcpu=sifive-u74 \
4+
;RUN: llc < %s -mtriple=riscv64 -mattr=+f -mcpu=sifive-u74 \
55
;RUN: -target-abi=lp64f | FileCheck %s --check-prefix=FUSION
6-
;RUN: llc < %s -mtriple=riscv64 -mattr=+f,+lui-addi-fusion,+use-postra-scheduler -mcpu=sifive-u74 \
6+
;RUN: llc < %s -mtriple=riscv64 -mattr=+f,+use-postra-scheduler -mcpu=sifive-u74 \
77
;RUN: -target-abi=lp64f | FileCheck %s --check-prefixes=FUSION-POSTRA
88

99
@.str = private constant [4 x i8] c"%f\0A\00", align 1
@@ -40,8 +40,8 @@ declare void @bar(ptr, float)
4040
define i32 @test_matint() {
4141
; NOFUSION-LABEL: test_matint:
4242
; NOFUSION: # %bb.0:
43-
; NOFUSION-NEXT: li a0, 1
44-
; NOFUSION-NEXT: slli a0, a0, 11
43+
; NOFUSION-NEXT: lui a0, 1
44+
; NOFUSION-NEXT: addiw a0, a0, -2048
4545
; NOFUSION-NEXT: ret
4646
;
4747
; FUSION-LABEL: test_matint:

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