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[AArch64] Add some uxtw peephole tests. NFC
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llvm/test/CodeGen/AArch64/peephole-sxtw.mir

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@@ -95,3 +95,57 @@ body: |
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B %bb.2
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...
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---
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name: removeUxtw
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x0
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; CHECK-LABEL: name: removeUxtw
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
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; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr $wzr, [[COPY1]]
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrr]], %subreg.sub_32
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32sp = COPY [[SUBREG_TO_REG]].sub_32
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; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY2]], 1, 0
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; CHECK-NEXT: $w0 = COPY [[ADDWri]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:gpr64 = COPY $x0
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%1:gpr32 = COPY %0.sub_32
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%2:gpr32 = ORRWrr $wzr, %1
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%3:gpr64 = SUBREG_TO_REG 0, %2, %subreg.sub_32
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%4:gpr32sp = COPY %3.sub_32
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%5:gpr32sp = ADDWri %4, 1, 0
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$w0 = COPY %5
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RET_ReallyLR implicit $w0
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...
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---
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name: extraUseOrr
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x0
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; CHECK-LABEL: name: extraUseOrr
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
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; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr $wzr, [[COPY1]]
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrr]], %subreg.sub_32
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32sp = COPY [[SUBREG_TO_REG]].sub_32
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; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY2]], 1, 0
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; CHECK-NEXT: $w0 = COPY [[ADDWri]]
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; CHECK-NEXT: $w1 = COPY [[ORRWrr]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:gpr64 = COPY $x0
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%1:gpr32 = COPY %0.sub_32
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%2:gpr32 = ORRWrr $wzr, %1
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%3:gpr64 = SUBREG_TO_REG 0, %2, %subreg.sub_32
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%4:gpr32sp = COPY %3.sub_32
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%5:gpr32sp = ADDWri %4, 1, 0
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$w0 = COPY %5
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$w1 = COPY %2
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RET_ReallyLR implicit $w0
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...

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