Skip to content

Commit 33afffe

Browse files
committed
Add RISC-V test case
1 parent b155053 commit 33afffe

File tree

1 file changed

+16
-0
lines changed

1 file changed

+16
-0
lines changed
Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,16 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2+
; RUN: opt < %s -S -p vector-combine -mtriple=riscv64 -mattr=+v | FileCheck %s
3+
4+
define <4 x i32> @add_constant_load(ptr %p) {
5+
; CHECK-LABEL: define <4 x i32> @add_constant_load(
6+
; CHECK-SAME: ptr [[P:%.*]]) #[[ATTR0:[0-9]+]] {
7+
; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[P]], align 4
8+
; CHECK-NEXT: [[V_SCALAR:%.*]] = add i32 [[X]], 42
9+
; CHECK-NEXT: [[V:%.*]] = insertelement <4 x i32> poison, i32 [[V_SCALAR]], i64 0
10+
; CHECK-NEXT: ret <4 x i32> [[V]]
11+
;
12+
%x = load i32, ptr %p
13+
%ins = insertelement <4 x i32> poison, i32 %x, i32 0
14+
%v = add <4 x i32> %ins, splat (i32 42)
15+
ret <4 x i32> %v
16+
}

0 commit comments

Comments
 (0)