Skip to content

Commit 33d7398

Browse files
ParkHanbumParkHanbum
committed
[AArch64] Add tests for prevent (shl (srl x, c1), c2) -> (and (shift x, c3)) when load
1 parent 40eca60 commit 33d7398

File tree

1 file changed

+145
-0
lines changed

1 file changed

+145
-0
lines changed

‎llvm/test/CodeGen/AArch64/arm64-fold-lshr.ll

Lines changed: 145 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,145 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2+
; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
3+
;
4+
5+
define i16 @load16_shr63(i64 %a, i64 %b, ptr %table) {
6+
; CHECK-LABEL: load16_shr63:
7+
; CHECK: // %bb.0: // %entry
8+
; CHECK-NEXT: mul x8, x1, x0
9+
; CHECK-NEXT: lsr x8, x8, #62
10+
; CHECK-NEXT: and x8, x8, #0x2
11+
; CHECK-NEXT: ldrh w0, [x2, x8]
12+
; CHECK-NEXT: ret
13+
entry:
14+
%mul = mul i64 %b, %a
15+
%shr = lshr i64 %mul, 63
16+
%arrayidx = getelementptr inbounds i16, ptr %table, i64 %shr
17+
%0 = load i16, ptr %arrayidx, align 2
18+
ret i16 %0
19+
}
20+
21+
define i16 @load16_shr2(i64 %a, i64 %b, ptr %table) {
22+
; CHECK-LABEL: load16_shr2:
23+
; CHECK: // %bb.0: // %entry
24+
; CHECK-NEXT: mul x8, x1, x0
25+
; CHECK-NEXT: lsr x8, x8, #1
26+
; CHECK-NEXT: and x8, x8, #0x7ffffffffffffffe
27+
; CHECK-NEXT: ldrh w0, [x2, x8]
28+
; CHECK-NEXT: ret
29+
entry:
30+
%mul = mul i64 %b, %a
31+
%shr = lshr i64 %mul, 2
32+
%arrayidx = getelementptr inbounds i16, ptr %table, i64 %shr
33+
%0 = load i16, ptr %arrayidx, align 2
34+
ret i16 %0
35+
}
36+
37+
define i16 @load16_shr1(i64 %a, i64 %b, ptr %table) {
38+
; CHECK-LABEL: load16_shr1:
39+
; CHECK: // %bb.0: // %entry
40+
; CHECK-NEXT: mul x8, x1, x0
41+
; CHECK-NEXT: and x8, x8, #0xfffffffffffffffe
42+
; CHECK-NEXT: ldrh w0, [x2, x8]
43+
; CHECK-NEXT: ret
44+
entry:
45+
%mul = mul i64 %b, %a
46+
%shr = lshr i64 %mul, 1
47+
%arrayidx = getelementptr inbounds i16, ptr %table, i64 %shr
48+
%0 = load i16, ptr %arrayidx, align 2
49+
ret i16 %0
50+
}
51+
52+
define i32 @load32_shr63(i64 %a, i64 %b, ptr %table) {
53+
; CHECK-LABEL: load32_shr63:
54+
; CHECK: // %bb.0: // %entry
55+
; CHECK-NEXT: mul x8, x1, x0
56+
; CHECK-NEXT: lsr x8, x8, #61
57+
; CHECK-NEXT: and x8, x8, #0x4
58+
; CHECK-NEXT: ldr w0, [x2, x8]
59+
; CHECK-NEXT: ret
60+
entry:
61+
%mul = mul i64 %b, %a
62+
%shr = lshr i64 %mul, 63
63+
%arrayidx = getelementptr inbounds i32, ptr %table, i64 %shr
64+
%0 = load i32, ptr %arrayidx, align 4
65+
ret i32 %0
66+
}
67+
68+
define i32 @load32_shr2(i64 %a, i64 %b, ptr %table) {
69+
; CHECK-LABEL: load32_shr2:
70+
; CHECK: // %bb.0: // %entry
71+
; CHECK-NEXT: mul x8, x1, x0
72+
; CHECK-NEXT: and x8, x8, #0xfffffffffffffffc
73+
; CHECK-NEXT: ldr w0, [x2, x8]
74+
; CHECK-NEXT: ret
75+
entry:
76+
%mul = mul i64 %b, %a
77+
%shr = lshr i64 %mul, 2
78+
%arrayidx = getelementptr inbounds i32, ptr %table, i64 %shr
79+
%0 = load i32, ptr %arrayidx, align 4
80+
ret i32 %0
81+
}
82+
83+
define i32 @load32_shr1(i64 %a, i64 %b, ptr %table) {
84+
; CHECK-LABEL: load32_shr1:
85+
; CHECK: // %bb.0: // %entry
86+
; CHECK-NEXT: mul x8, x1, x0
87+
; CHECK-NEXT: lsl x8, x8, #1
88+
; CHECK-NEXT: and x8, x8, #0xfffffffffffffffc
89+
; CHECK-NEXT: ldr w0, [x2, x8]
90+
; CHECK-NEXT: ret
91+
entry:
92+
%mul = mul i64 %b, %a
93+
%shr = lshr i64 %mul, 1
94+
%arrayidx = getelementptr inbounds i32, ptr %table, i64 %shr
95+
%0 = load i32, ptr %arrayidx, align 4
96+
ret i32 %0
97+
}
98+
99+
define i64 @load64_shr63(i64 %a, i64 %b, ptr %table) {
100+
; CHECK-LABEL: load64_shr63:
101+
; CHECK: // %bb.0: // %entry
102+
; CHECK-NEXT: mul x8, x1, x0
103+
; CHECK-NEXT: lsr x8, x8, #60
104+
; CHECK-NEXT: and x8, x8, #0x8
105+
; CHECK-NEXT: ldr x0, [x2, x8]
106+
; CHECK-NEXT: ret
107+
entry:
108+
%mul = mul i64 %b, %a
109+
%shr = lshr i64 %mul, 63
110+
%arrayidx = getelementptr inbounds i64, ptr %table, i64 %shr
111+
%0 = load i64, ptr %arrayidx, align 8
112+
ret i64 %0
113+
}
114+
115+
define i64 @load64_shr2(i64 %a, i64 %b, ptr %table) {
116+
; CHECK-LABEL: load64_shr2:
117+
; CHECK: // %bb.0: // %entry
118+
; CHECK-NEXT: mul x8, x1, x0
119+
; CHECK-NEXT: lsl x8, x8, #1
120+
; CHECK-NEXT: and x8, x8, #0xfffffffffffffff8
121+
; CHECK-NEXT: ldr x0, [x2, x8]
122+
; CHECK-NEXT: ret
123+
entry:
124+
%mul = mul i64 %b, %a
125+
%shr = lshr i64 %mul, 2
126+
%arrayidx = getelementptr inbounds i64, ptr %table, i64 %shr
127+
%0 = load i64, ptr %arrayidx, align 8
128+
ret i64 %0
129+
}
130+
131+
define i64 @load64_shr1(i64 %a, i64 %b, ptr %table) {
132+
; CHECK-LABEL: load64_shr1:
133+
; CHECK: // %bb.0: // %entry
134+
; CHECK-NEXT: mul x8, x1, x0
135+
; CHECK-NEXT: lsl x8, x8, #2
136+
; CHECK-NEXT: and x8, x8, #0xfffffffffffffff8
137+
; CHECK-NEXT: ldr x0, [x2, x8]
138+
; CHECK-NEXT: ret
139+
entry:
140+
%mul = mul i64 %b, %a
141+
%shr = lshr i64 %mul, 1
142+
%arrayidx = getelementptr inbounds i64, ptr %table, i64 %shr
143+
%0 = load i64, ptr %arrayidx, align 8
144+
ret i64 %0
145+
}

0 commit comments

Comments
 (0)