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[AMDGPU][SIPreEmitPeephole] pre-commit tests: mustRetainExeczBranch: use a cost model
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‎llvm/test/CodeGen/AMDGPU/amdgpu-demote-scc-branches.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10,GFX1010 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GFX10,GFX1030 %s
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define void @convergent_cmp_no_metadata(i32 noundef inreg %value, ptr addrspace(8) nocapture writeonly inreg %res, i32 noundef inreg %v_offset, i32 noundef inreg %0, i32 noundef inreg %flag) {
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; GFX10-LABEL: convergent_cmp_no_metadata:
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; GFX10: ; %bb.0: ; %entry
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_cmp_lt_i32 s21, 1
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; GFX10-NEXT: s_cbranch_scc1 .LBB0_2
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; GFX10-NEXT: ; %bb.1: ; %if.then
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; GFX10-NEXT: v_mov_b32_e32 v0, s6
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; GFX10-NEXT: v_mov_b32_e32 v1, s19
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; GFX10-NEXT: s_mov_b32 s11, s18
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; GFX10-NEXT: s_mov_b32 s10, s17
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; GFX10-NEXT: s_mov_b32 s9, s16
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; GFX10-NEXT: s_mov_b32 s8, s7
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; GFX10-NEXT: buffer_store_dword v0, v1, s[8:11], 0 offen
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; GFX10-NEXT: .LBB0_2: ; %if.end
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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entry:
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%cmp = icmp sgt i32 %flag, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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tail call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 %value, ptr addrspace(8) %res, i32 %v_offset, i32 0, i32 0)
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br label %if.end
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if.end:
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call void @llvm.amdgcn.s.waitcnt(i32 0)
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ret void
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}
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define void @convergent_cmp_unprofitable(i32 noundef inreg %value, ptr addrspace(8) nocapture writeonly inreg %res, i32 noundef inreg %v_offset, i32 noundef inreg %0, i32 noundef inreg %flag) {
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; GFX10-LABEL: convergent_cmp_unprofitable:
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; GFX10: ; %bb.0: ; %entry
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_cmp_lt_i32 s21, 1
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; GFX10-NEXT: s_cbranch_scc1 .LBB1_2
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; GFX10-NEXT: ; %bb.1: ; %if.then
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; GFX10-NEXT: v_mov_b32_e32 v0, s6
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; GFX10-NEXT: v_mov_b32_e32 v1, s19
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; GFX10-NEXT: s_mov_b32 s11, s18
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; GFX10-NEXT: s_mov_b32 s10, s17
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; GFX10-NEXT: s_mov_b32 s9, s16
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; GFX10-NEXT: s_mov_b32 s8, s7
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; GFX10-NEXT: buffer_store_dword v0, v1, s[8:11], 0 offen
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; GFX10-NEXT: .LBB1_2: ; %if.end
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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entry:
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%cmp = icmp sgt i32 %flag, 0
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br i1 %cmp, label %if.then, label %if.end, !prof !0
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if.then:
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tail call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 %value, ptr addrspace(8) %res, i32 %v_offset, i32 0, i32 0)
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br label %if.end
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if.end:
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call void @llvm.amdgcn.s.waitcnt(i32 0)
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ret void
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}
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define void @convergent_cmp_profitable(i32 noundef inreg %value, ptr addrspace(8) nocapture writeonly inreg %res, i32 noundef inreg %v_offset, i32 noundef inreg %0, i32 noundef inreg %flag) {
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; GFX10-LABEL: convergent_cmp_profitable:
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; GFX10: ; %bb.0: ; %entry
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_cmp_lt_i32 s21, 1
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; GFX10-NEXT: s_cbranch_scc1 .LBB2_2
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; GFX10-NEXT: ; %bb.1: ; %if.then
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; GFX10-NEXT: v_mov_b32_e32 v0, s6
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; GFX10-NEXT: v_mov_b32_e32 v1, s19
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; GFX10-NEXT: s_mov_b32 s11, s18
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; GFX10-NEXT: s_mov_b32 s10, s17
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; GFX10-NEXT: s_mov_b32 s9, s16
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; GFX10-NEXT: s_mov_b32 s8, s7
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; GFX10-NEXT: buffer_store_dword v0, v1, s[8:11], 0 offen
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; GFX10-NEXT: .LBB2_2: ; %if.end
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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entry:
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%cmp = icmp sgt i32 %flag, 0
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br i1 %cmp, label %if.then, label %if.end, !prof !1
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if.then:
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tail call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 %value, ptr addrspace(8) %res, i32 %v_offset, i32 0, i32 0)
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br label %if.end
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if.end:
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call void @llvm.amdgcn.s.waitcnt(i32 0)
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ret void
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}
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define void @divergent_cmp_no_metadata(i32 noundef inreg %value, ptr addrspace(8) nocapture writeonly inreg %res, i32 noundef inreg %v_offset, i32 noundef inreg %0, i32 noundef inreg %flag) {
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; GFX1010-LABEL: divergent_cmp_no_metadata:
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; GFX1010: ; %bb.0: ; %entry
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; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX1010-NEXT: v_and_b32_e32 v0, 0x3ff, v31
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; GFX1010-NEXT: v_cmp_gt_i32_e32 vcc_lo, s21, v0
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; GFX1010-NEXT: s_and_saveexec_b32 s4, vcc_lo
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; GFX1010-NEXT: s_cbranch_execz .LBB3_2
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; GFX1010-NEXT: ; %bb.1: ; %if.then
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; GFX1010-NEXT: v_mov_b32_e32 v0, s6
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; GFX1010-NEXT: v_mov_b32_e32 v1, s19
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; GFX1010-NEXT: s_mov_b32 s11, s18
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; GFX1010-NEXT: s_mov_b32 s10, s17
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; GFX1010-NEXT: s_mov_b32 s9, s16
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; GFX1010-NEXT: s_mov_b32 s8, s7
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; GFX1010-NEXT: buffer_store_dword v0, v1, s[8:11], 0 offen
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; GFX1010-NEXT: .LBB3_2: ; %if.end
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; GFX1010-NEXT: s_waitcnt_depctr 0xffe3
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; GFX1010-NEXT: s_or_b32 exec_lo, exec_lo, s4
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; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX1010-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX1030-LABEL: divergent_cmp_no_metadata:
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; GFX1030: ; %bb.0: ; %entry
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; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX1030-NEXT: v_and_b32_e32 v0, 0x3ff, v31
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; GFX1030-NEXT: s_mov_b32 s4, exec_lo
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; GFX1030-NEXT: v_cmpx_gt_i32_e64 s21, v0
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; GFX1030-NEXT: s_cbranch_execz .LBB3_2
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; GFX1030-NEXT: ; %bb.1: ; %if.then
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; GFX1030-NEXT: v_mov_b32_e32 v0, s6
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; GFX1030-NEXT: v_mov_b32_e32 v1, s19
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; GFX1030-NEXT: s_mov_b32 s11, s18
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; GFX1030-NEXT: s_mov_b32 s10, s17
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; GFX1030-NEXT: s_mov_b32 s9, s16
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; GFX1030-NEXT: s_mov_b32 s8, s7
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; GFX1030-NEXT: buffer_store_dword v0, v1, s[8:11], 0 offen
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; GFX1030-NEXT: .LBB3_2: ; %if.end
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; GFX1030-NEXT: s_or_b32 exec_lo, exec_lo, s4
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; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX1030-NEXT: s_setpc_b64 s[30:31]
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entry:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%cmp = icmp sgt i32 %flag, %id
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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tail call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 %value, ptr addrspace(8) %res, i32 %v_offset, i32 0, i32 0)
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br label %if.end
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if.end:
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call void @llvm.amdgcn.s.waitcnt(i32 0)
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ret void
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}
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define void @divergent_cmp_unprofitable(i32 noundef inreg %value, ptr addrspace(8) nocapture writeonly inreg %res, i32 noundef inreg %v_offset, i32 noundef inreg %0, i32 noundef inreg %flag) {
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; GFX1010-LABEL: divergent_cmp_unprofitable:
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; GFX1010: ; %bb.0: ; %entry
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; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX1010-NEXT: v_and_b32_e32 v0, 0x3ff, v31
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; GFX1010-NEXT: v_cmp_gt_i32_e32 vcc_lo, s21, v0
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; GFX1010-NEXT: s_and_saveexec_b32 s4, vcc_lo
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; GFX1010-NEXT: s_cbranch_execz .LBB4_2
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; GFX1010-NEXT: ; %bb.1: ; %if.then
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; GFX1010-NEXT: v_mov_b32_e32 v0, s6
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; GFX1010-NEXT: v_mov_b32_e32 v1, s19
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; GFX1010-NEXT: s_mov_b32 s11, s18
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; GFX1010-NEXT: s_mov_b32 s10, s17
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; GFX1010-NEXT: s_mov_b32 s9, s16
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; GFX1010-NEXT: s_mov_b32 s8, s7
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; GFX1010-NEXT: buffer_store_dword v0, v1, s[8:11], 0 offen
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; GFX1010-NEXT: .LBB4_2: ; %if.end
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; GFX1010-NEXT: s_waitcnt_depctr 0xffe3
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; GFX1010-NEXT: s_or_b32 exec_lo, exec_lo, s4
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; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX1010-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX1030-LABEL: divergent_cmp_unprofitable:
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; GFX1030: ; %bb.0: ; %entry
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; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX1030-NEXT: v_and_b32_e32 v0, 0x3ff, v31
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; GFX1030-NEXT: s_mov_b32 s4, exec_lo
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; GFX1030-NEXT: v_cmpx_gt_i32_e64 s21, v0
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; GFX1030-NEXT: s_cbranch_execz .LBB4_2
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; GFX1030-NEXT: ; %bb.1: ; %if.then
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; GFX1030-NEXT: v_mov_b32_e32 v0, s6
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; GFX1030-NEXT: v_mov_b32_e32 v1, s19
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; GFX1030-NEXT: s_mov_b32 s11, s18
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; GFX1030-NEXT: s_mov_b32 s10, s17
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; GFX1030-NEXT: s_mov_b32 s9, s16
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; GFX1030-NEXT: s_mov_b32 s8, s7
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; GFX1030-NEXT: buffer_store_dword v0, v1, s[8:11], 0 offen
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; GFX1030-NEXT: .LBB4_2: ; %if.end
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; GFX1030-NEXT: s_or_b32 exec_lo, exec_lo, s4
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; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX1030-NEXT: s_setpc_b64 s[30:31]
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entry:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%cmp = icmp sgt i32 %flag, %id
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br i1 %cmp, label %if.then, label %if.end, !prof !0
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if.then:
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tail call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 %value, ptr addrspace(8) %res, i32 %v_offset, i32 0, i32 0)
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br label %if.end
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if.end:
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call void @llvm.amdgcn.s.waitcnt(i32 0)
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ret void
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}
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define void @divergent_cmp_profitable(i32 noundef inreg %value, ptr addrspace(8) nocapture writeonly inreg %res, i32 noundef inreg %v_offset, i32 noundef inreg %0, i32 noundef inreg %flag) {
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; GFX1010-LABEL: divergent_cmp_profitable:
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; GFX1010: ; %bb.0: ; %entry
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; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX1010-NEXT: v_and_b32_e32 v0, 0x3ff, v31
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; GFX1010-NEXT: v_cmp_gt_i32_e32 vcc_lo, s21, v0
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; GFX1010-NEXT: s_and_saveexec_b32 s4, vcc_lo
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; GFX1010-NEXT: s_cbranch_execz .LBB5_2
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; GFX1010-NEXT: ; %bb.1: ; %if.then
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; GFX1010-NEXT: v_mov_b32_e32 v0, s6
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; GFX1010-NEXT: v_mov_b32_e32 v1, s19
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; GFX1010-NEXT: s_mov_b32 s11, s18
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; GFX1010-NEXT: s_mov_b32 s10, s17
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; GFX1010-NEXT: s_mov_b32 s9, s16
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; GFX1010-NEXT: s_mov_b32 s8, s7
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; GFX1010-NEXT: buffer_store_dword v0, v1, s[8:11], 0 offen
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; GFX1010-NEXT: .LBB5_2: ; %if.end
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; GFX1010-NEXT: s_waitcnt_depctr 0xffe3
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; GFX1010-NEXT: s_or_b32 exec_lo, exec_lo, s4
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; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX1010-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX1030-LABEL: divergent_cmp_profitable:
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; GFX1030: ; %bb.0: ; %entry
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; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX1030-NEXT: v_and_b32_e32 v0, 0x3ff, v31
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; GFX1030-NEXT: s_mov_b32 s4, exec_lo
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; GFX1030-NEXT: v_cmpx_gt_i32_e64 s21, v0
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; GFX1030-NEXT: s_cbranch_execz .LBB5_2
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; GFX1030-NEXT: ; %bb.1: ; %if.then
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; GFX1030-NEXT: v_mov_b32_e32 v0, s6
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; GFX1030-NEXT: v_mov_b32_e32 v1, s19
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; GFX1030-NEXT: s_mov_b32 s11, s18
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; GFX1030-NEXT: s_mov_b32 s10, s17
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; GFX1030-NEXT: s_mov_b32 s9, s16
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; GFX1030-NEXT: s_mov_b32 s8, s7
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; GFX1030-NEXT: buffer_store_dword v0, v1, s[8:11], 0 offen
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; GFX1030-NEXT: .LBB5_2: ; %if.end
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; GFX1030-NEXT: s_or_b32 exec_lo, exec_lo, s4
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; GFX1030-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX1030-NEXT: s_setpc_b64 s[30:31]
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entry:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%cmp = icmp sgt i32 %flag, %id
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br i1 %cmp, label %if.then, label %if.end, !prof !1
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if.then:
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tail call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 %value, ptr addrspace(8) %res, i32 %v_offset, i32 0, i32 0)
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br label %if.end
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if.end:
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call void @llvm.amdgcn.s.waitcnt(i32 0)
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ret void
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}
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declare void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32, ptr addrspace(8) nocapture writeonly, i32, i32, i32 immarg)
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declare void @llvm.amdgcn.s.waitcnt(i32)
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declare i32 @llvm.amdgcn.workitem.id.x()
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!0 = !{!"branch_weights", i32 1000, i32 1000}
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!1 = !{!"branch_weights", i32 2000, i32 1}

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