[LSR] Regenerate test checks (NFC)

Check output IR instead of debug output. The debug output will
change in an upcoming patch in an irrecoverable way.

Author: nikic

llvm/test/Transforms/LoopStrengthReduce/Power/incomplete-phi.ll

@@ -1,9 +1,9 @@
-; REQUIRES: asserts
-; RUN: opt -loop-reduce -debug-only=loop-reduce -S  < %s 2>&1 | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt -loop-reduce -S  < %s 2>&1 | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-n32:64"
 target triple = "powerpc64le-unknown-linux-gnu"
-;
+
 ; %lsr.iv2 and %lsr.iv10 are in same bb, but they are not equal since start
 ; value are different.
 ;
@@ -14,17 +14,44 @@ target triple = "powerpc64le-unknown-linux-gnu"
 ; %lsr.iv10 = phi [0 x %0]* [ %2, %bb18 ], [ %arg, %bb ]
 ;
 ; Make sure two incomplete phis will not be marked as congruent.
-;
-; CHECK: One incomplete PHI is found:   %[[IV:.*]] = phi ptr
-; CHECK: One incomplete PHI is found:   %[[IV2:.*]] = phi ptr
-; CHECK-NOT: Eliminated congruent iv:  %[[IV]]
-; CHECK-NOT: Original iv: %[[IV2]]
-; CHECK-NOT: Eliminated congruent iv:  %[[IV2]]
-; CHECK-NOT: Original iv: %[[IV]]
 
 %0 = type <{ float }>
 
 define void @foo(ptr %arg) {
+; CHECK-LABEL: define void @foo(
+; CHECK-SAME: ptr [[ARG:%.*]]) {
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    [[I:%.*]] = getelementptr [0 x %0], ptr [[ARG]], i64 0, i64 -1
+; CHECK-NEXT:    [[I2:%.*]] = getelementptr i8, ptr [[I]], i64 4
+; CHECK-NEXT:    [[SCEVGEP:%.*]] = getelementptr i8, ptr [[ARG]], i64 396
+; CHECK-NEXT:    br label [[BB3:%.*]]
+; CHECK:       bb3:
+; CHECK-NEXT:    [[LSR_IV7:%.*]] = phi ptr [ [[SCEVGEP8:%.*]], [[BB18:%.*]] ], [ [[I2]], [[BB:%.*]] ]
+; CHECK-NEXT:    [[LSR_IV5:%.*]] = phi i64 [ [[LSR_IV_NEXT6:%.*]], [[BB18]] ], [ 4, [[BB]] ]
+; CHECK-NEXT:    [[LSR_IV1:%.*]] = phi ptr [ [[SCEVGEP2:%.*]], [[BB18]] ], [ [[SCEVGEP]], [[BB]] ]
+; CHECK-NEXT:    br i1 true, label [[BB22_PREHEADER:%.*]], label [[BB9_PREHEADER:%.*]]
+; CHECK:       bb9.preheader:
+; CHECK-NEXT:    br label [[BB9:%.*]]
+; CHECK:       bb9:
+; CHECK-NEXT:    [[LSR_IV9:%.*]] = phi ptr [ [[LSR_IV7]], [[BB9_PREHEADER]] ], [ [[SCEVGEP10:%.*]], [[BB9]] ]
+; CHECK-NEXT:    store <4 x float> undef, ptr [[LSR_IV9]], align 4
+; CHECK-NEXT:    [[SCEVGEP10]] = getelementptr i8, ptr [[LSR_IV9]], i64 128
+; CHECK-NEXT:    br i1 true, label [[BB17:%.*]], label [[BB9]]
+; CHECK:       bb17:
+; CHECK-NEXT:    br i1 false, label [[BB18]], label [[BB22_PREHEADER]]
+; CHECK:       bb22.preheader:
+; CHECK-NEXT:    br label [[BB22:%.*]]
+; CHECK:       bb18:
+; CHECK-NEXT:    [[LSR_IV_NEXT6]] = add nuw nsw i64 [[LSR_IV5]], 4
+; CHECK-NEXT:    [[SCEVGEP2]] = getelementptr i8, ptr [[LSR_IV1]], i64 [[LSR_IV5]]
+; CHECK-NEXT:    [[SCEVGEP8]] = getelementptr i8, ptr [[LSR_IV7]], i64 [[LSR_IV5]]
+; CHECK-NEXT:    br label [[BB3]]
+; CHECK:       bb22:
+; CHECK-NEXT:    [[LSR_IV3:%.*]] = phi ptr [ [[LSR_IV1]], [[BB22_PREHEADER]] ], [ [[SCEVGEP4:%.*]], [[BB22]] ]
+; CHECK-NEXT:    store float undef, ptr [[LSR_IV3]], align 4
+; CHECK-NEXT:    [[SCEVGEP4]] = getelementptr i8, ptr [[LSR_IV3]], i64 4
+; CHECK-NEXT:    br label [[BB22]]
+;
 bb:
   %i = getelementptr inbounds [0 x %0], ptr %arg, i64 0, i64 -1
   %i2 = getelementptr i8, ptr %i, i64 4