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[CodeGenPrepare] Transform shl X, cttz(Y) to mul (Y & -Y), X if cttz is unsupported
1 parent 8555432 commit 370a2a7

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2 files changed

+124
-142
lines changed

2 files changed

+124
-142
lines changed

‎llvm/lib/CodeGen/CodeGenPrepare.cpp

Lines changed: 23 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8396,7 +8396,29 @@ bool CodeGenPrepare::optimizeInst(Instruction *I, ModifyDT &ModifiedDT) {
83968396
return true;
83978397

83988398
switch (I->getOpcode()) {
8399-
case Instruction::Shl:
8399+
case Instruction::Shl: {
8400+
// shl X, cttz(Y) -> mul (Y & -Y), X if cttz is unsupported on the target.
8401+
Value *Y;
8402+
if (match(I->getOperand(1),
8403+
m_OneUse(m_Intrinsic<Intrinsic::cttz>(m_Value(Y))))) {
8404+
EVT VT = TLI->getValueType(*DL, Y->getType());
8405+
if (!TLI->isOperationLegalOrCustom(ISD::CTTZ, VT) &&
8406+
TLI->isOperationLegalOrCustom(ISD::MUL, VT)) {
8407+
IRBuilder<> Builder(I);
8408+
Value *NegY = Builder.CreateNeg(Y);
8409+
Value *Power2 = Builder.CreateAnd(Y, NegY);
8410+
Value *New = Builder.CreateMul(Power2, I->getOperand(0), "",
8411+
/*HasNUW=*/I->hasNoUnsignedWrap(),
8412+
/*HasNSW=*/false);
8413+
replaceAllUsesWith(I, New, FreshBBs, IsHugeFunc);
8414+
RecursivelyDeleteTriviallyDeadInstructions(
8415+
I, TLInfo, nullptr,
8416+
[&](Value *V) { removeAllAssertingVHReferences(V); });
8417+
return true;
8418+
}
8419+
}
8420+
}
8421+
[[fallthrough]]
84008422
case Instruction::LShr:
84018423
case Instruction::AShr:
84028424
return optimizeShiftInst(cast<BinaryOperator>(I));

‎llvm/test/CodeGen/RISCV/shl-cttz.ll

Lines changed: 101 additions & 141 deletions
Original file line numberDiff line numberDiff line change
@@ -17,15 +17,7 @@ define i32 @shl_cttz_i32(i32 %x, i32 %y) {
1717
; RV32I: # %bb.0: # %entry
1818
; RV32I-NEXT: neg a2, a1
1919
; RV32I-NEXT: and a1, a1, a2
20-
; RV32I-NEXT: lui a2, 30667
21-
; RV32I-NEXT: addi a2, a2, 1329
22-
; RV32I-NEXT: mul a1, a1, a2
23-
; RV32I-NEXT: srli a1, a1, 27
24-
; RV32I-NEXT: lui a2, %hi(.LCPI0_0)
25-
; RV32I-NEXT: addi a2, a2, %lo(.LCPI0_0)
26-
; RV32I-NEXT: add a1, a2, a1
27-
; RV32I-NEXT: lbu a1, 0(a1)
28-
; RV32I-NEXT: sll a0, a0, a1
20+
; RV32I-NEXT: mul a0, a1, a0
2921
; RV32I-NEXT: ret
3022
;
3123
; RV32ZBB-LABEL: shl_cttz_i32:
@@ -34,26 +26,33 @@ define i32 @shl_cttz_i32(i32 %x, i32 %y) {
3426
; RV32ZBB-NEXT: sll a0, a0, a1
3527
; RV32ZBB-NEXT: ret
3628
;
37-
; RV64I-LABEL: shl_cttz_i32:
38-
; RV64I: # %bb.0: # %entry
39-
; RV64I-NEXT: negw a2, a1
40-
; RV64I-NEXT: and a1, a1, a2
41-
; RV64I-NEXT: lui a2, 30667
42-
; RV64I-NEXT: addi a2, a2, 1329
43-
; RV64I-NEXT: mul a1, a1, a2
44-
; RV64I-NEXT: srliw a1, a1, 27
45-
; RV64I-NEXT: lui a2, %hi(.LCPI0_0)
46-
; RV64I-NEXT: addi a2, a2, %lo(.LCPI0_0)
47-
; RV64I-NEXT: add a1, a2, a1
48-
; RV64I-NEXT: lbu a1, 0(a1)
49-
; RV64I-NEXT: sllw a0, a0, a1
50-
; RV64I-NEXT: ret
29+
; RV64IILLEGALI32-LABEL: shl_cttz_i32:
30+
; RV64IILLEGALI32: # %bb.0: # %entry
31+
; RV64IILLEGALI32-NEXT: negw a2, a1
32+
; RV64IILLEGALI32-NEXT: and a1, a1, a2
33+
; RV64IILLEGALI32-NEXT: lui a2, 30667
34+
; RV64IILLEGALI32-NEXT: addi a2, a2, 1329
35+
; RV64IILLEGALI32-NEXT: mul a1, a1, a2
36+
; RV64IILLEGALI32-NEXT: srliw a1, a1, 27
37+
; RV64IILLEGALI32-NEXT: lui a2, %hi(.LCPI0_0)
38+
; RV64IILLEGALI32-NEXT: addi a2, a2, %lo(.LCPI0_0)
39+
; RV64IILLEGALI32-NEXT: add a1, a2, a1
40+
; RV64IILLEGALI32-NEXT: lbu a1, 0(a1)
41+
; RV64IILLEGALI32-NEXT: sllw a0, a0, a1
42+
; RV64IILLEGALI32-NEXT: ret
5143
;
5244
; RV64ZBB-LABEL: shl_cttz_i32:
5345
; RV64ZBB: # %bb.0: # %entry
5446
; RV64ZBB-NEXT: ctzw a1, a1
5547
; RV64ZBB-NEXT: sllw a0, a0, a1
5648
; RV64ZBB-NEXT: ret
49+
;
50+
; RV64ILEGALI32-LABEL: shl_cttz_i32:
51+
; RV64ILEGALI32: # %bb.0: # %entry
52+
; RV64ILEGALI32-NEXT: negw a2, a1
53+
; RV64ILEGALI32-NEXT: and a1, a1, a2
54+
; RV64ILEGALI32-NEXT: mulw a0, a1, a0
55+
; RV64ILEGALI32-NEXT: ret
5756
entry:
5857
%cttz = call i32 @llvm.cttz.i32(i32 %y, i1 true)
5958
%res = shl i32 %x, %cttz
@@ -65,16 +64,7 @@ define i32 @shl_cttz_constant_i32(i32 %y) {
6564
; RV32I: # %bb.0: # %entry
6665
; RV32I-NEXT: neg a1, a0
6766
; RV32I-NEXT: and a0, a0, a1
68-
; RV32I-NEXT: lui a1, 30667
69-
; RV32I-NEXT: addi a1, a1, 1329
70-
; RV32I-NEXT: mul a0, a0, a1
71-
; RV32I-NEXT: srli a0, a0, 27
72-
; RV32I-NEXT: lui a1, %hi(.LCPI1_0)
73-
; RV32I-NEXT: addi a1, a1, %lo(.LCPI1_0)
74-
; RV32I-NEXT: add a0, a1, a0
75-
; RV32I-NEXT: lbu a0, 0(a0)
76-
; RV32I-NEXT: li a1, 4
77-
; RV32I-NEXT: sll a0, a1, a0
67+
; RV32I-NEXT: slli a0, a0, 2
7868
; RV32I-NEXT: ret
7969
;
8070
; RV32ZBB-LABEL: shl_cttz_constant_i32:
@@ -84,28 +74,35 @@ define i32 @shl_cttz_constant_i32(i32 %y) {
8474
; RV32ZBB-NEXT: sll a0, a1, a0
8575
; RV32ZBB-NEXT: ret
8676
;
87-
; RV64I-LABEL: shl_cttz_constant_i32:
88-
; RV64I: # %bb.0: # %entry
89-
; RV64I-NEXT: negw a1, a0
90-
; RV64I-NEXT: and a0, a0, a1
91-
; RV64I-NEXT: lui a1, 30667
92-
; RV64I-NEXT: addi a1, a1, 1329
93-
; RV64I-NEXT: mul a0, a0, a1
94-
; RV64I-NEXT: srliw a0, a0, 27
95-
; RV64I-NEXT: lui a1, %hi(.LCPI1_0)
96-
; RV64I-NEXT: addi a1, a1, %lo(.LCPI1_0)
97-
; RV64I-NEXT: add a0, a1, a0
98-
; RV64I-NEXT: lbu a0, 0(a0)
99-
; RV64I-NEXT: li a1, 4
100-
; RV64I-NEXT: sllw a0, a1, a0
101-
; RV64I-NEXT: ret
77+
; RV64IILLEGALI32-LABEL: shl_cttz_constant_i32:
78+
; RV64IILLEGALI32: # %bb.0: # %entry
79+
; RV64IILLEGALI32-NEXT: negw a1, a0
80+
; RV64IILLEGALI32-NEXT: and a0, a0, a1
81+
; RV64IILLEGALI32-NEXT: lui a1, 30667
82+
; RV64IILLEGALI32-NEXT: addi a1, a1, 1329
83+
; RV64IILLEGALI32-NEXT: mul a0, a0, a1
84+
; RV64IILLEGALI32-NEXT: srliw a0, a0, 27
85+
; RV64IILLEGALI32-NEXT: lui a1, %hi(.LCPI1_0)
86+
; RV64IILLEGALI32-NEXT: addi a1, a1, %lo(.LCPI1_0)
87+
; RV64IILLEGALI32-NEXT: add a0, a1, a0
88+
; RV64IILLEGALI32-NEXT: lbu a0, 0(a0)
89+
; RV64IILLEGALI32-NEXT: li a1, 4
90+
; RV64IILLEGALI32-NEXT: sllw a0, a1, a0
91+
; RV64IILLEGALI32-NEXT: ret
10292
;
10393
; RV64ZBB-LABEL: shl_cttz_constant_i32:
10494
; RV64ZBB: # %bb.0: # %entry
10595
; RV64ZBB-NEXT: ctzw a0, a0
10696
; RV64ZBB-NEXT: li a1, 4
10797
; RV64ZBB-NEXT: sllw a0, a1, a0
10898
; RV64ZBB-NEXT: ret
99+
;
100+
; RV64ILEGALI32-LABEL: shl_cttz_constant_i32:
101+
; RV64ILEGALI32: # %bb.0: # %entry
102+
; RV64ILEGALI32-NEXT: negw a1, a0
103+
; RV64ILEGALI32-NEXT: and a0, a0, a1
104+
; RV64ILEGALI32-NEXT: slliw a0, a0, 2
105+
; RV64ILEGALI32-NEXT: ret
109106
entry:
110107
%cttz = call i32 @llvm.cttz.i32(i32 %y, i1 true)
111108
%res = shl i32 4, %cttz
@@ -117,15 +114,7 @@ define i32 @shl_cttz_nuw_i32(i32 %x, i32 %y) {
117114
; RV32I: # %bb.0: # %entry
118115
; RV32I-NEXT: neg a2, a1
119116
; RV32I-NEXT: and a1, a1, a2
120-
; RV32I-NEXT: lui a2, 30667
121-
; RV32I-NEXT: addi a2, a2, 1329
122-
; RV32I-NEXT: mul a1, a1, a2
123-
; RV32I-NEXT: srli a1, a1, 27
124-
; RV32I-NEXT: lui a2, %hi(.LCPI2_0)
125-
; RV32I-NEXT: addi a2, a2, %lo(.LCPI2_0)
126-
; RV32I-NEXT: add a1, a2, a1
127-
; RV32I-NEXT: lbu a1, 0(a1)
128-
; RV32I-NEXT: sll a0, a0, a1
117+
; RV32I-NEXT: mul a0, a1, a0
129118
; RV32I-NEXT: ret
130119
;
131120
; RV32ZBB-LABEL: shl_cttz_nuw_i32:
@@ -134,26 +123,33 @@ define i32 @shl_cttz_nuw_i32(i32 %x, i32 %y) {
134123
; RV32ZBB-NEXT: sll a0, a0, a1
135124
; RV32ZBB-NEXT: ret
136125
;
137-
; RV64I-LABEL: shl_cttz_nuw_i32:
138-
; RV64I: # %bb.0: # %entry
139-
; RV64I-NEXT: negw a2, a1
140-
; RV64I-NEXT: and a1, a1, a2
141-
; RV64I-NEXT: lui a2, 30667
142-
; RV64I-NEXT: addi a2, a2, 1329
143-
; RV64I-NEXT: mul a1, a1, a2
144-
; RV64I-NEXT: srliw a1, a1, 27
145-
; RV64I-NEXT: lui a2, %hi(.LCPI2_0)
146-
; RV64I-NEXT: addi a2, a2, %lo(.LCPI2_0)
147-
; RV64I-NEXT: add a1, a2, a1
148-
; RV64I-NEXT: lbu a1, 0(a1)
149-
; RV64I-NEXT: sllw a0, a0, a1
150-
; RV64I-NEXT: ret
126+
; RV64IILLEGALI32-LABEL: shl_cttz_nuw_i32:
127+
; RV64IILLEGALI32: # %bb.0: # %entry
128+
; RV64IILLEGALI32-NEXT: negw a2, a1
129+
; RV64IILLEGALI32-NEXT: and a1, a1, a2
130+
; RV64IILLEGALI32-NEXT: lui a2, 30667
131+
; RV64IILLEGALI32-NEXT: addi a2, a2, 1329
132+
; RV64IILLEGALI32-NEXT: mul a1, a1, a2
133+
; RV64IILLEGALI32-NEXT: srliw a1, a1, 27
134+
; RV64IILLEGALI32-NEXT: lui a2, %hi(.LCPI2_0)
135+
; RV64IILLEGALI32-NEXT: addi a2, a2, %lo(.LCPI2_0)
136+
; RV64IILLEGALI32-NEXT: add a1, a2, a1
137+
; RV64IILLEGALI32-NEXT: lbu a1, 0(a1)
138+
; RV64IILLEGALI32-NEXT: sllw a0, a0, a1
139+
; RV64IILLEGALI32-NEXT: ret
151140
;
152141
; RV64ZBB-LABEL: shl_cttz_nuw_i32:
153142
; RV64ZBB: # %bb.0: # %entry
154143
; RV64ZBB-NEXT: ctzw a1, a1
155144
; RV64ZBB-NEXT: sllw a0, a0, a1
156145
; RV64ZBB-NEXT: ret
146+
;
147+
; RV64ILEGALI32-LABEL: shl_cttz_nuw_i32:
148+
; RV64ILEGALI32: # %bb.0: # %entry
149+
; RV64ILEGALI32-NEXT: negw a2, a1
150+
; RV64ILEGALI32-NEXT: and a1, a1, a2
151+
; RV64ILEGALI32-NEXT: mulw a0, a1, a0
152+
; RV64ILEGALI32-NEXT: ret
157153
entry:
158154
%cttz = call i32 @llvm.cttz.i32(i32 %y, i1 true)
159155
%res = shl nuw i32 %x, %cttz
@@ -165,15 +161,7 @@ define i32 @shl_cttz_nsw_i32(i32 %x, i32 %y) {
165161
; RV32I: # %bb.0: # %entry
166162
; RV32I-NEXT: neg a2, a1
167163
; RV32I-NEXT: and a1, a1, a2
168-
; RV32I-NEXT: lui a2, 30667
169-
; RV32I-NEXT: addi a2, a2, 1329
170-
; RV32I-NEXT: mul a1, a1, a2
171-
; RV32I-NEXT: srli a1, a1, 27
172-
; RV32I-NEXT: lui a2, %hi(.LCPI3_0)
173-
; RV32I-NEXT: addi a2, a2, %lo(.LCPI3_0)
174-
; RV32I-NEXT: add a1, a2, a1
175-
; RV32I-NEXT: lbu a1, 0(a1)
176-
; RV32I-NEXT: sll a0, a0, a1
164+
; RV32I-NEXT: mul a0, a1, a0
177165
; RV32I-NEXT: ret
178166
;
179167
; RV32ZBB-LABEL: shl_cttz_nsw_i32:
@@ -182,26 +170,33 @@ define i32 @shl_cttz_nsw_i32(i32 %x, i32 %y) {
182170
; RV32ZBB-NEXT: sll a0, a0, a1
183171
; RV32ZBB-NEXT: ret
184172
;
185-
; RV64I-LABEL: shl_cttz_nsw_i32:
186-
; RV64I: # %bb.0: # %entry
187-
; RV64I-NEXT: negw a2, a1
188-
; RV64I-NEXT: and a1, a1, a2
189-
; RV64I-NEXT: lui a2, 30667
190-
; RV64I-NEXT: addi a2, a2, 1329
191-
; RV64I-NEXT: mul a1, a1, a2
192-
; RV64I-NEXT: srliw a1, a1, 27
193-
; RV64I-NEXT: lui a2, %hi(.LCPI3_0)
194-
; RV64I-NEXT: addi a2, a2, %lo(.LCPI3_0)
195-
; RV64I-NEXT: add a1, a2, a1
196-
; RV64I-NEXT: lbu a1, 0(a1)
197-
; RV64I-NEXT: sllw a0, a0, a1
198-
; RV64I-NEXT: ret
173+
; RV64IILLEGALI32-LABEL: shl_cttz_nsw_i32:
174+
; RV64IILLEGALI32: # %bb.0: # %entry
175+
; RV64IILLEGALI32-NEXT: negw a2, a1
176+
; RV64IILLEGALI32-NEXT: and a1, a1, a2
177+
; RV64IILLEGALI32-NEXT: lui a2, 30667
178+
; RV64IILLEGALI32-NEXT: addi a2, a2, 1329
179+
; RV64IILLEGALI32-NEXT: mul a1, a1, a2
180+
; RV64IILLEGALI32-NEXT: srliw a1, a1, 27
181+
; RV64IILLEGALI32-NEXT: lui a2, %hi(.LCPI3_0)
182+
; RV64IILLEGALI32-NEXT: addi a2, a2, %lo(.LCPI3_0)
183+
; RV64IILLEGALI32-NEXT: add a1, a2, a1
184+
; RV64IILLEGALI32-NEXT: lbu a1, 0(a1)
185+
; RV64IILLEGALI32-NEXT: sllw a0, a0, a1
186+
; RV64IILLEGALI32-NEXT: ret
199187
;
200188
; RV64ZBB-LABEL: shl_cttz_nsw_i32:
201189
; RV64ZBB: # %bb.0: # %entry
202190
; RV64ZBB-NEXT: ctzw a1, a1
203191
; RV64ZBB-NEXT: sllw a0, a0, a1
204192
; RV64ZBB-NEXT: ret
193+
;
194+
; RV64ILEGALI32-LABEL: shl_cttz_nsw_i32:
195+
; RV64ILEGALI32: # %bb.0: # %entry
196+
; RV64ILEGALI32-NEXT: negw a2, a1
197+
; RV64ILEGALI32-NEXT: and a1, a1, a2
198+
; RV64ILEGALI32-NEXT: mulw a0, a1, a0
199+
; RV64ILEGALI32-NEXT: ret
205200
entry:
206201
%cttz = call i32 @llvm.cttz.i32(i32 %y, i1 true)
207202
%res = shl nsw i32 %x, %cttz
@@ -388,17 +383,9 @@ define i64 @shl_cttz_i64(i64 %x, i64 %y) {
388383
;
389384
; RV64I-LABEL: shl_cttz_i64:
390385
; RV64I: # %bb.0: # %entry
391-
; RV64I-NEXT: lui a2, %hi(.LCPI5_0)
392-
; RV64I-NEXT: ld a2, %lo(.LCPI5_0)(a2)
393-
; RV64I-NEXT: neg a3, a1
394-
; RV64I-NEXT: and a1, a1, a3
395-
; RV64I-NEXT: mul a1, a1, a2
396-
; RV64I-NEXT: srli a1, a1, 58
397-
; RV64I-NEXT: lui a2, %hi(.LCPI5_1)
398-
; RV64I-NEXT: addi a2, a2, %lo(.LCPI5_1)
399-
; RV64I-NEXT: add a1, a2, a1
400-
; RV64I-NEXT: lbu a1, 0(a1)
401-
; RV64I-NEXT: sll a0, a0, a1
386+
; RV64I-NEXT: neg a2, a1
387+
; RV64I-NEXT: and a1, a1, a2
388+
; RV64I-NEXT: mul a0, a1, a0
402389
; RV64I-NEXT: ret
403390
;
404391
; RV64ZBB-LABEL: shl_cttz_i64:
@@ -481,18 +468,9 @@ define i64 @shl_cttz_constant_i64(i64 %y) {
481468
;
482469
; RV64I-LABEL: shl_cttz_constant_i64:
483470
; RV64I: # %bb.0: # %entry
484-
; RV64I-NEXT: lui a1, %hi(.LCPI6_0)
485-
; RV64I-NEXT: ld a1, %lo(.LCPI6_0)(a1)
486-
; RV64I-NEXT: neg a2, a0
487-
; RV64I-NEXT: and a0, a0, a2
488-
; RV64I-NEXT: mul a0, a0, a1
489-
; RV64I-NEXT: srli a0, a0, 58
490-
; RV64I-NEXT: lui a1, %hi(.LCPI6_1)
491-
; RV64I-NEXT: addi a1, a1, %lo(.LCPI6_1)
492-
; RV64I-NEXT: add a0, a1, a0
493-
; RV64I-NEXT: lbu a0, 0(a0)
494-
; RV64I-NEXT: li a1, 4
495-
; RV64I-NEXT: sll a0, a1, a0
471+
; RV64I-NEXT: neg a1, a0
472+
; RV64I-NEXT: and a0, a0, a1
473+
; RV64I-NEXT: slli a0, a0, 2
496474
; RV64I-NEXT: ret
497475
;
498476
; RV64ZBB-LABEL: shl_cttz_constant_i64:
@@ -578,17 +556,9 @@ define i64 @shl_cttz_nuw_i64(i64 %x, i64 %y) {
578556
;
579557
; RV64I-LABEL: shl_cttz_nuw_i64:
580558
; RV64I: # %bb.0: # %entry
581-
; RV64I-NEXT: lui a2, %hi(.LCPI7_0)
582-
; RV64I-NEXT: ld a2, %lo(.LCPI7_0)(a2)
583-
; RV64I-NEXT: neg a3, a1
584-
; RV64I-NEXT: and a1, a1, a3
585-
; RV64I-NEXT: mul a1, a1, a2
586-
; RV64I-NEXT: srli a1, a1, 58
587-
; RV64I-NEXT: lui a2, %hi(.LCPI7_1)
588-
; RV64I-NEXT: addi a2, a2, %lo(.LCPI7_1)
589-
; RV64I-NEXT: add a1, a2, a1
590-
; RV64I-NEXT: lbu a1, 0(a1)
591-
; RV64I-NEXT: sll a0, a0, a1
559+
; RV64I-NEXT: neg a2, a1
560+
; RV64I-NEXT: and a1, a1, a2
561+
; RV64I-NEXT: mul a0, a1, a0
592562
; RV64I-NEXT: ret
593563
;
594564
; RV64ZBB-LABEL: shl_cttz_nuw_i64:
@@ -673,17 +643,9 @@ define i64 @shl_cttz_nsw_i64(i64 %x, i64 %y) {
673643
;
674644
; RV64I-LABEL: shl_cttz_nsw_i64:
675645
; RV64I: # %bb.0: # %entry
676-
; RV64I-NEXT: lui a2, %hi(.LCPI8_0)
677-
; RV64I-NEXT: ld a2, %lo(.LCPI8_0)(a2)
678-
; RV64I-NEXT: neg a3, a1
679-
; RV64I-NEXT: and a1, a1, a3
680-
; RV64I-NEXT: mul a1, a1, a2
681-
; RV64I-NEXT: srli a1, a1, 58
682-
; RV64I-NEXT: lui a2, %hi(.LCPI8_1)
683-
; RV64I-NEXT: addi a2, a2, %lo(.LCPI8_1)
684-
; RV64I-NEXT: add a1, a2, a1
685-
; RV64I-NEXT: lbu a1, 0(a1)
686-
; RV64I-NEXT: sll a0, a0, a1
646+
; RV64I-NEXT: neg a2, a1
647+
; RV64I-NEXT: and a1, a1, a2
648+
; RV64I-NEXT: mul a0, a1, a0
687649
; RV64I-NEXT: ret
688650
;
689651
; RV64ZBB-LABEL: shl_cttz_nsw_i64:
@@ -866,7 +828,5 @@ entry:
866828
declare void @use32(i32 signext)
867829
declare void @use64(i64)
868830
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
869-
; RV64IILLEGALI32: {{.*}}
870-
; RV64ILEGALI32: {{.*}}
871831
; RV64ZBBILLEGALI32: {{.*}}
872832
; RV64ZBBLEGALI32: {{.*}}

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