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JoshuaMBaJoshuaMBa
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Merge branch 'llvm:main' into vector_update
2 parents e9fe448 + ead486c commit 378604d

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5 files changed

+162
-17
lines changed

5 files changed

+162
-17
lines changed

‎clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@
1414
//
1515
//===---------------------------------------------------------------------===//
1616

17+
#include "clang/Basic/TargetID.h"
1718
#include "clang/Basic/Version.h"
1819
#include "llvm/ADT/MapVector.h"
1920
#include "llvm/BinaryFormat/Magic.h"
@@ -668,7 +669,8 @@ std::unique_ptr<lto::LTO> createLTO(
668669
ModuleHook Hook = [](size_t, const Module &) { return true; }) {
669670
const llvm::Triple Triple(Args.getLastArgValue(OPT_triple_EQ));
670671
// We need to remove AMD's target-id from the processor if present.
671-
StringRef Arch = Args.getLastArgValue(OPT_arch_EQ).split(":").first;
672+
StringRef TargetID = Args.getLastArgValue(OPT_arch_EQ);
673+
StringRef Arch = clang::getProcessorFromTargetID(Triple, TargetID);
672674
lto::Config Conf;
673675
lto::ThinBackend Backend;
674676
// TODO: Handle index-only thin-LTO
@@ -712,7 +714,7 @@ std::unique_ptr<lto::LTO> createLTO(
712714

713715
if (SaveTemps) {
714716
std::string TempName = (sys::path::filename(ExecutableName) + "." +
715-
Triple.getTriple() + "." + Arch)
717+
Triple.getTriple() + "." + TargetID)
716718
.str();
717719
Conf.PostInternalizeModuleHook = [=](size_t Task, const Module &M) {
718720
std::string File =

‎compiler-rt/lib/scudo/standalone/string_utils.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@ class ScopedString {
4040
void appendString(int Width, int MaxChars, const char *S);
4141
void appendPointer(u64 ptr_value);
4242

43-
Vector<char> String;
43+
Vector<char, 256> String;
4444
};
4545

4646
void Printf(const char *Format, ...) FORMAT(1, 2);

‎compiler-rt/lib/scudo/standalone/tests/vector_test.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
1111
#include "vector.h"
1212

1313
TEST(ScudoVectorTest, Basic) {
14-
scudo::Vector<int> V;
14+
scudo::Vector<int, 64U> V;
1515
EXPECT_EQ(V.size(), 0U);
1616
V.push_back(42);
1717
EXPECT_EQ(V.size(), 1U);
@@ -23,7 +23,7 @@ TEST(ScudoVectorTest, Basic) {
2323
}
2424

2525
TEST(ScudoVectorTest, Stride) {
26-
scudo::Vector<scudo::uptr> V;
26+
scudo::Vector<scudo::uptr, 32U> V;
2727
for (scudo::uptr I = 0; I < 1000; I++) {
2828
V.push_back(I);
2929
EXPECT_EQ(V.size(), I + 1U);
@@ -34,7 +34,7 @@ TEST(ScudoVectorTest, Stride) {
3434
}
3535

3636
TEST(ScudoVectorTest, ResizeReduction) {
37-
scudo::Vector<int> V;
37+
scudo::Vector<int, 64U> V;
3838
V.push_back(0);
3939
V.push_back(0);
4040
EXPECT_EQ(V.size(), 2U);
@@ -48,7 +48,7 @@ TEST(ScudoVectorTest, ResizeReduction) {
4848

4949
// Verify that if the reallocate fails, nothing new is added.
5050
TEST(ScudoVectorTest, ReallocateFails) {
51-
scudo::Vector<char> V;
51+
scudo::Vector<char, 256U> V;
5252
scudo::uptr capacity = V.capacity();
5353

5454
// Get the current address space size.

‎compiler-rt/lib/scudo/standalone/vector.h

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,6 @@
99
#ifndef SCUDO_VECTOR_H_
1010
#define SCUDO_VECTOR_H_
1111

12-
#include "common.h"
1312
#include "mem_map.h"
1413

1514
#include <string.h>
@@ -22,7 +21,7 @@ namespace scudo {
2221
// implementation supports only POD types.
2322
//
2423
// NOTE: This class is not meant to be used directly, use Vector<T> instead.
25-
template <typename T, size_t StaticCapacityBytes> class VectorNoCtor {
24+
template <typename T, size_t StaticNumEntries> class VectorNoCtor {
2625
public:
2726
T &operator[](uptr I) {
2827
DCHECK_LT(I, Size);
@@ -117,21 +116,21 @@ template <typename T, size_t StaticCapacityBytes> class VectorNoCtor {
117116
uptr CapacityBytes = 0;
118117
uptr Size = 0;
119118

120-
T LocalData[StaticCapacityBytes / sizeof(T)] = {};
119+
T LocalData[StaticNumEntries] = {};
121120
MemMapT ExternalBuffer;
122121
};
123122

124-
template <typename T, size_t StaticCapacityBytes = 256U>
125-
class Vector : public VectorNoCtor<T, StaticCapacityBytes> {
123+
template <typename T, size_t StaticNumEntries>
124+
class Vector : public VectorNoCtor<T, StaticNumEntries> {
126125
public:
127-
// Static capacity should be non-zero
128-
static_assert(StaticCapacityBytes > 0U);
129-
constexpr Vector() { VectorNoCtor<T, StaticCapacityBytes>::init(); }
126+
static_assert(StaticNumEntries > 0U,
127+
"Vector must have a non-zero number of static entries.");
128+
constexpr Vector() { VectorNoCtor<T, StaticNumEntries>::init(); }
130129
explicit Vector(uptr Count) {
131-
VectorNoCtor<T, StaticCapacityBytes>::init(Count);
130+
VectorNoCtor<T, StaticNumEntries>::init(Count);
132131
this->resize(Count);
133132
}
134-
~Vector() { VectorNoCtor<T, StaticCapacityBytes>::destroy(); }
133+
~Vector() { VectorNoCtor<T, StaticNumEntries>::destroy(); }
135134
// Disallow copies and moves.
136135
Vector(const Vector &) = delete;
137136
Vector &operator=(const Vector &) = delete;

‎llvm/test/Transforms/InstCombine/vector-logical-reductions.ll

Lines changed: 144 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,15 @@ define i1 @reduction_logical_or(<4 x i1> %x) {
1111
ret i1 %r
1212
}
1313

14+
define i1 @reduction_logical_or_nxv2i1(<vscale x 2 x i1> %x) {
15+
; CHECK-LABEL: @reduction_logical_or_nxv2i1(
16+
; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1> [[X:%.*]])
17+
; CHECK-NEXT: ret i1 [[R]]
18+
;
19+
%r = call i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1> %x)
20+
ret i1 %r
21+
}
22+
1423
define i1 @reduction_logical_and(<4 x i1> %x) {
1524
; CHECK-LABEL: @reduction_logical_and(
1625
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[X:%.*]] to i4
@@ -21,6 +30,131 @@ define i1 @reduction_logical_and(<4 x i1> %x) {
2130
ret i1 %r
2231
}
2332

33+
define i1 @reduction_logical_and_nxv2i1(<vscale x 2 x i1> %x) {
34+
; CHECK-LABEL: @reduction_logical_and_nxv2i1(
35+
; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.vector.reduce.and.nxv2i1(<vscale x 2 x i1> [[X:%.*]])
36+
; CHECK-NEXT: ret i1 [[R]]
37+
;
38+
%r = call i1 @llvm.vector.reduce.and.nxv2i1(<vscale x 2 x i1> %x)
39+
ret i1 %r
40+
}
41+
42+
define i1 @reduction_logical_mul(<2 x i1> %x) {
43+
; CHECK-LABEL: @reduction_logical_mul(
44+
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i1> [[X:%.*]] to i2
45+
; CHECK-NEXT: [[R:%.*]] = icmp eq i2 [[TMP1]], -1
46+
; CHECK-NEXT: ret i1 [[R]]
47+
;
48+
%r = call i1 @llvm.vector.reduce.mul.v4i1(<2 x i1> %x)
49+
ret i1 %r
50+
}
51+
52+
define i1 @reduction_logical_mul_nxv2i1(<vscale x 2 x i1> %x) {
53+
; CHECK-LABEL: @reduction_logical_mul_nxv2i1(
54+
; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.vector.reduce.mul.nxv2i1(<vscale x 2 x i1> [[X:%.*]])
55+
; CHECK-NEXT: ret i1 [[R]]
56+
;
57+
%r = call i1 @llvm.vector.reduce.mul.nxv2i1(<vscale x 2 x i1> %x)
58+
ret i1 %r
59+
}
60+
61+
define i1 @reduction_logical_xor(<2 x i1> %x) {
62+
; CHECK-LABEL: @reduction_logical_xor(
63+
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i1> [[X:%.*]] to i2
64+
; CHECK-NEXT: [[TMP2:%.*]] = call range(i2 0, -1) i2 @llvm.ctpop.i2(i2 [[TMP1]])
65+
; CHECK-NEXT: [[R:%.*]] = trunc i2 [[TMP2]] to i1
66+
; CHECK-NEXT: ret i1 [[R]]
67+
;
68+
%r = call i1 @llvm.vector.reduce.xor.v4i1(<2 x i1> %x)
69+
ret i1 %r
70+
}
71+
72+
define i1 @reduction_logical_xor_nxv2i1(<vscale x 2 x i1> %x) {
73+
; CHECK-LABEL: @reduction_logical_xor_nxv2i1(
74+
; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.vector.reduce.xor.nxv2i1(<vscale x 2 x i1> [[X:%.*]])
75+
; CHECK-NEXT: ret i1 [[R]]
76+
;
77+
%r = call i1 @llvm.vector.reduce.xor.nxv2i1(<vscale x 2 x i1> %x)
78+
ret i1 %r
79+
}
80+
81+
define i1 @reduction_logical_smin(<2 x i1> %x) {
82+
; CHECK-LABEL: @reduction_logical_smin(
83+
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i1> [[X:%.*]] to i2
84+
; CHECK-NEXT: [[R:%.*]] = icmp ne i2 [[TMP1]], 0
85+
; CHECK-NEXT: ret i1 [[R]]
86+
;
87+
%r = call i1 @llvm.vector.reduce.smin.v4i1(<2 x i1> %x)
88+
ret i1 %r
89+
}
90+
91+
define i1 @reduction_logical_smin_nxv2i1(<vscale x 2 x i1> %x) {
92+
; CHECK-LABEL: @reduction_logical_smin_nxv2i1(
93+
; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.vector.reduce.smin.nxv2i1(<vscale x 2 x i1> [[X:%.*]])
94+
; CHECK-NEXT: ret i1 [[R]]
95+
;
96+
%r = call i1 @llvm.vector.reduce.smin.nxv2i1(<vscale x 2 x i1> %x)
97+
ret i1 %r
98+
}
99+
100+
define i1 @reduction_logical_smax(<2 x i1> %x) {
101+
; CHECK-LABEL: @reduction_logical_smax(
102+
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i1> [[X:%.*]] to i2
103+
; CHECK-NEXT: [[R:%.*]] = icmp eq i2 [[TMP1]], -1
104+
; CHECK-NEXT: ret i1 [[R]]
105+
;
106+
%r = call i1 @llvm.vector.reduce.smax.v4i1(<2 x i1> %x)
107+
ret i1 %r
108+
}
109+
110+
define i1 @reduction_logical_smax_nxv2i1(<vscale x 2 x i1> %x) {
111+
; CHECK-LABEL: @reduction_logical_smax_nxv2i1(
112+
; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.vector.reduce.smax.nxv2i1(<vscale x 2 x i1> [[X:%.*]])
113+
; CHECK-NEXT: ret i1 [[R]]
114+
;
115+
%r = call i1 @llvm.vector.reduce.smax.nxv2i1(<vscale x 2 x i1> %x)
116+
ret i1 %r
117+
}
118+
119+
define i1 @reduction_logical_umin(<2 x i1> %x) {
120+
; CHECK-LABEL: @reduction_logical_umin(
121+
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i1> [[X:%.*]] to i2
122+
; CHECK-NEXT: [[R:%.*]] = icmp eq i2 [[TMP1]], -1
123+
; CHECK-NEXT: ret i1 [[R]]
124+
;
125+
%r = call i1 @llvm.vector.reduce.umin.v4i1(<2 x i1> %x)
126+
ret i1 %r
127+
}
128+
129+
define i1 @reduction_logical_umin_nxv2i1(<vscale x 2 x i1> %x) {
130+
; CHECK-LABEL: @reduction_logical_umin_nxv2i1(
131+
; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.vector.reduce.umin.nxv2i1(<vscale x 2 x i1> [[X:%.*]])
132+
; CHECK-NEXT: ret i1 [[R]]
133+
;
134+
%r = call i1 @llvm.vector.reduce.umin.nxv2i1(<vscale x 2 x i1> %x)
135+
ret i1 %r
136+
}
137+
138+
define i1 @reduction_logical_umax(<2 x i1> %x) {
139+
; CHECK-LABEL: @reduction_logical_umax(
140+
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i1> [[X:%.*]] to i2
141+
; CHECK-NEXT: [[R:%.*]] = icmp ne i2 [[TMP1]], 0
142+
; CHECK-NEXT: ret i1 [[R]]
143+
;
144+
%r = call i1 @llvm.vector.reduce.umax.v4i1(<2 x i1> %x)
145+
ret i1 %r
146+
}
147+
148+
define i1 @reduction_logical_umax_nxv2i1(<vscale x 2 x i1> %x) {
149+
; CHECK-LABEL: @reduction_logical_umax_nxv2i1(
150+
; CHECK-NEXT: [[R:%.*]] = call i1 @llvm.vector.reduce.umax.nxv2i1(<vscale x 2 x i1> [[X:%.*]])
151+
; CHECK-NEXT: ret i1 [[R]]
152+
;
153+
%r = call i1 @llvm.vector.reduce.umax.nxv2i1(<vscale x 2 x i1> %x)
154+
ret i1 %r
155+
}
156+
157+
24158
define i1 @reduction_logical_or_reverse_nxv2i1(<vscale x 2 x i1> %p) {
25159
; CHECK-LABEL: @reduction_logical_or_reverse_nxv2i1(
26160
; CHECK-NEXT: [[RED:%.*]] = call i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1> [[P:%.*]])
@@ -93,5 +227,15 @@ declare i1 @llvm.vector.reduce.and.nxv2i1(<vscale x 2 x i1>)
93227
declare i1 @llvm.vector.reduce.and.v2i1(<2 x i1>)
94228
declare i1 @llvm.vector.reduce.xor.nxv2i1(<vscale x 2 x i1>)
95229
declare i1 @llvm.vector.reduce.xor.v2i1(<2 x i1>)
230+
declare i1 @llvm.vector.reduce.mul.nxv2i1(<vscale x 2 x i1>)
231+
declare i1 @llvm.vector.reduce.mul.v2i1(<2 x i1>)
232+
declare i1 @llvm.vector.reduce.smin.nxv2i1(<vscale x 2 x i1>)
233+
declare i1 @llvm.vector.reduce.smin.v2i1(<2 x i1>)
234+
declare i1 @llvm.vector.reduce.smax.nxv2i1(<vscale x 2 x i1>)
235+
declare i1 @llvm.vector.reduce.smax.v2i1(<2 x i1>)
236+
declare i1 @llvm.vector.reduce.umin.nxv2i1(<vscale x 2 x i1>)
237+
declare i1 @llvm.vector.reduce.umin.v2i1(<2 x i1>)
238+
declare i1 @llvm.vector.reduce.umax.nxv2i1(<vscale x 2 x i1>)
239+
declare i1 @llvm.vector.reduce.umax.v2i1(<2 x i1>)
96240
declare <vscale x 2 x i1> @llvm.vector.reverse.nxv2i1(<vscale x 2 x i1>)
97241
declare <2 x i1> @llvm.vector.reverse.v2i1(<2 x i1>)

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